QSPI Interface

Driver API for QSPI (plib_qspi.h) More...

Data Structures
struct	QSPI_INSTRUCTION_FRAME
	Description of one Serial Memory mode instruction frame (QSPI_IFR). More...

Macros
#define	QSPI_MEMORY_BASE_ADDRESS   (QSPIMEM_ADDR)
	Base address of the memory-mapped QSPI window (QSPIMEM).
#define	QSPI_MEMORY_SIZE   (QSPIMEM_SIZE)
	Size of the memory-mapped QSPI window in bytes.
#define	QSPI_BAUD_MAX   (QSPI_SCR_SCBR_Msk >> QSPI_SCR_SCBR_Pos)
	Maximum value of the serial clock baud rate divider (QSPI_SCR.SCBR).
#define	QSPI_DUMMY_CYCLES_MAX   (QSPI_IFR_NBDUM_Msk >> QSPI_IFR_NBDUM_Pos)
	Maximum number of dummy cycles (QSPI_IFR.NBDUM).
#define	QSPI_DELAY_MAX   (QSPI_MR_DLYBCT_Msk >> QSPI_MR_DLYBCT_Pos)
	Maximum value of any of the QSPI delay fields (DLYBS, DLYBCT, DLYCS).
#define	QSPI_WPMR_UNLOCK_KEY   (QSPI_WPMR_WPKEY_PASSWD_Val)
	Password that must accompany a write to QSPI_WPMR.WPEN.
#define	QSPI_INTERRUPT_NONE   (0x00000000U)
#define	QSPI_INTERRUPT_RDRF   (QSPI_IER_RDRF_Msk)
#define	QSPI_INTERRUPT_TDRE   (QSPI_IER_TDRE_Msk)
#define	QSPI_INTERRUPT_TXEMPTY   (QSPI_IER_TXEMPTY_Msk)
#define	QSPI_INTERRUPT_OVRES   (QSPI_IER_OVRES_Msk)
#define	QSPI_INTERRUPT_CSR   (QSPI_IER_CSR_Msk)
#define	QSPI_INTERRUPT_CSS   (QSPI_IER_CSS_Msk)
#define	QSPI_INTERRUPT_INSTRE   (QSPI_IER_INSTRE_Msk)
#define	QSPI_INTERRUPT_ALL   (QSPI_IER_Msk)
#define	QSPI_STATUS_FLAG_NONE   (0x00000000U)
#define	QSPI_STATUS_FLAG_RDRF   (QSPI_SR_RDRF_Msk)
#define	QSPI_STATUS_FLAG_TDRE   (QSPI_SR_TDRE_Msk)
#define	QSPI_STATUS_FLAG_TXEMPTY   (QSPI_SR_TXEMPTY_Msk)
#define	QSPI_STATUS_FLAG_OVRES   (QSPI_SR_OVRES_Msk)
#define	QSPI_STATUS_FLAG_CSR   (QSPI_SR_CSR_Msk)
#define	QSPI_STATUS_FLAG_CSS   (QSPI_SR_CSS_Msk)
#define	QSPI_STATUS_FLAG_INSTRE   (QSPI_SR_INSTRE_Msk)
#define	QSPI_STATUS_FLAG_QSPIENS   (QSPI_SR_QSPIENS_Msk)
#define	QSPI_STATUS_FLAG_ALL   (QSPI_SR_Msk)
#define	QSPI_STATUS_FLAG_READ_TO_CLEAR    (QSPI_SR_OVRES_Msk | QSPI_SR_CSR_Msk | QSPI_SR_INSTRE_Msk)
	The subset of QSPI_SR flags that are cleared by reading the register.
#define	QSPI_ERROR_NONE   (0x00U)
#define	QSPI_ERROR_OVERRUN   (0x01U)

Typedefs
typedef uint32_t	QSPI_INTERRUPT_SOURCE
	QSPI interrupt source bitmask type.
typedef uint32_t	QSPI_STATUS_FLAG
	QSPI status flag bitmask type (QSPI_SR).
typedef uint32_t	QSPI_ERROR
	QSPI error status bitmask type.
typedef void(*	QSPI_CALLBACK) (QSPI_STATUS_FLAG status)
	QSPI callback function type.

Enumerations
enum	QSPI_HWREG_STATUS {   QSPI_HWREG_OK = 0 , QSPI_HWREG_ERROR , QSPI_HWREG_INVALID_PARAM , QSPI_HWREG_TIMEOUT ,   QSPI_HWREG_BUSY , QSPI_HWREG_UNSUPPORTED }
	Result of a QSPI hardware register operation. More...
enum	QSPI_OPERATING_MODE { QSPI_OPERATING_MODE_SPI = (int32_t)QSPI_MR_SMM_SPI_Val , QSPI_OPERATING_MODE_MEMORY = (int32_t)QSPI_MR_SMM_MEMORY_Val }
	QSPI operating mode (QSPI_MR.SMM). More...
enum	QSPI_CHIP_SELECT_MODE { QSPI_CHIP_SELECT_MODE_NOT_RELOADED = (int32_t)QSPI_MR_CSMODE_NOT_RELOADED_Val , QSPI_CHIP_SELECT_MODE_LASTXFER = (int32_t)QSPI_MR_CSMODE_LASTXFER_Val , QSPI_CHIP_SELECT_MODE_SYSTEMATICALLY = (int32_t)QSPI_MR_CSMODE_SYSTEMATICALLY_Val }
	Chip select behaviour at the end of a transfer (QSPI_MR.CSMODE). More...
enum	QSPI_TRANSFER_SIZE {   QSPI_TRANSFER_SIZE_8BIT = 0 , QSPI_TRANSFER_SIZE_9BIT = 1 , QSPI_TRANSFER_SIZE_10BIT = 2 , QSPI_TRANSFER_SIZE_11BIT = 3 ,   QSPI_TRANSFER_SIZE_12BIT = 4 , QSPI_TRANSFER_SIZE_13BIT = 5 , QSPI_TRANSFER_SIZE_14BIT = 6 , QSPI_TRANSFER_SIZE_15BIT = 7 ,   QSPI_TRANSFER_SIZE_16BIT = 8 }
	Number of bits per transfer in SPI mode (QSPI_MR.NBBITS). More...
enum	QSPI_CLOCK_POLARITY { QSPI_CLOCK_POLARITY_IDLE_LOW = 0 , QSPI_CLOCK_POLARITY_IDLE_HIGH = 1 }
	Inactive state of QSCK (QSPI_SCR.CPOL). More...
enum	QSPI_CLOCK_PHASE { QSPI_CLOCK_PHASE_CAPTURE_LEADING = 0 , QSPI_CLOCK_PHASE_CAPTURE_TRAILING = 1 }
	QSCK edge on which data is captured (QSPI_SCR.CPHA). More...
enum	QSPI_LANE_WIDTH {   QSPI_LANE_WIDTH_SINGLE_BIT_SPI = (int32_t)QSPI_IFR_WIDTH_SINGLE_BIT_SPI_Val , QSPI_LANE_WIDTH_DUAL_OUTPUT = (int32_t)QSPI_IFR_WIDTH_DUAL_OUTPUT_Val , QSPI_LANE_WIDTH_QUAD_OUTPUT = (int32_t)QSPI_IFR_WIDTH_QUAD_OUTPUT_Val , QSPI_LANE_WIDTH_DUAL_IO = (int32_t)QSPI_IFR_WIDTH_DUAL_IO_Val ,   QSPI_LANE_WIDTH_QUAD_IO = (int32_t)QSPI_IFR_WIDTH_QUAD_IO_Val , QSPI_LANE_WIDTH_DUAL_CMD = (int32_t)QSPI_IFR_WIDTH_DUAL_CMD_Val , QSPI_LANE_WIDTH_QUAD_CMD = (int32_t)QSPI_IFR_WIDTH_QUAD_CMD_Val }
	Number of data lanes used by each phase of an instruction frame (QSPI_IFR.WIDTH). More...
enum	QSPI_ADDRESS_LENGTH { QSPI_ADDRESS_LENGTH_24BIT = (int32_t)QSPI_IFR_ADDRL_24_BIT_Val , QSPI_ADDRESS_LENGTH_32BIT = (int32_t)QSPI_IFR_ADDRL_32_BIT_Val }
	Length of the address phase of an instruction frame (QSPI_IFR.ADDRL). More...
enum	QSPI_OPTION_LENGTH { QSPI_OPTION_LENGTH_1BIT = (int32_t)QSPI_IFR_OPTL_OPTION_1BIT_Val , QSPI_OPTION_LENGTH_2BIT = (int32_t)QSPI_IFR_OPTL_OPTION_2BIT_Val , QSPI_OPTION_LENGTH_4BIT = (int32_t)QSPI_IFR_OPTL_OPTION_4BIT_Val , QSPI_OPTION_LENGTH_8BIT = (int32_t)QSPI_IFR_OPTL_OPTION_8BIT_Val }
	Length of the option phase of an instruction frame (QSPI_IFR.OPTL). More...
enum	QSPI_TRANSFER_TYPE { QSPI_TRANSFER_TYPE_READ = (int32_t)QSPI_IFR_TFRTYP_TRSFR_READ_Val , QSPI_TRANSFER_TYPE_READ_MEMORY = (int32_t)QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY_Val , QSPI_TRANSFER_TYPE_WRITE = (int32_t)QSPI_IFR_TFRTYP_TRSFR_WRITE_Val , QSPI_TRANSFER_TYPE_WRITE_MEMORY = (int32_t)QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY_Val }
	Kind of data transfer performed by an instruction frame (QSPI_IFR.TFRTYP). More...

Functions
void	QSPI_Enable (void)
	Enables the QSPI (QSPI_CR.QSPIEN).
void	QSPI_Disable (void)
	Disables the QSPI (QSPI_CR.QSPIDIS).
bool	QSPI_IsEnabled (void)
	Checks whether the QSPI is enabled (QSPI_SR.QSPIENS).
void	QSPI_ResetSoftware (void)
	Performs a software reset of the QSPI (QSPI_CR.SWRST).
void	QSPI_EndTransfer (void)
	Marks the current transfer as the last one (QSPI_CR.LASTXFER).
void	QSPI_SetOperatingMode (QSPI_OPERATING_MODE mode)
	Selects SPI mode or Serial Memory mode (QSPI_MR.SMM).
void	QSPI_SetChipSelectMode (QSPI_CHIP_SELECT_MODE mode)
	Sets the chip select mode (QSPI_MR.CSMODE).
void	QSPI_SetTransferSize (QSPI_TRANSFER_SIZE size)
	Sets the number of bits per transfer in SPI mode (QSPI_MR.NBBITS).
void	QSPI_SetLoopback (bool is_enabled)
	Enables or disables the local loopback path (QSPI_MR.LLB).
void	QSPI_SetDelayBetweenConsecutiveTransfers (uint8_t delay)
	Sets the delay between consecutive transfers (QSPI_MR.DLYBCT).
void	QSPI_SetDelayBetweenChipSelects (uint8_t delay)
	Sets the minimum inactive chip select delay (QSPI_MR.DLYCS).
void	QSPI_Send (uint16_t data)
	Writes one character to the transmit holding register (QSPI_TDR.TD).
uint16_t	QSPI_Receive (void)
	Reads one character from the receive holding register (QSPI_RDR.RD).
bool	QSPI_TxIsReady (void)
	Checks whether QSPI_TDR can accept a character (QSPI_SR.TDRE).
bool	QSPI_RxIsReady (void)
	Checks whether QSPI_RDR holds an unread character (QSPI_SR.RDRF).
bool	QSPI_TransferIsComplete (void)
	Checks whether all requested transfers have completed (QSPI_SR.TXEMPTY).
void	QSPI_SetClockPolarity (QSPI_CLOCK_POLARITY polarity)
	Sets the inactive state of QSCK (QSPI_SCR.CPOL).
void	QSPI_SetClockPhase (QSPI_CLOCK_PHASE phase)
	Sets the QSCK edge on which data is captured (QSPI_SCR.CPHA).
void	QSPI_SetDelayBeforeSck (uint8_t delay)
	Sets the delay before the first QSCK edge (QSPI_SCR.DLYBS).
QSPI_HWREG_STATUS	QSPI_SetBusSpeed (uint32_t bus_speed, uint32_t clk_frequency)
	Sets the serial clock baud rate (QSPI_SCR.SCBR).
uint32_t	QSPI_GetBusSpeed (uint32_t clk_frequency)
	Gets the serial clock baud rate currently configured.
void	QSPI_SetInstructionAddress (uint32_t address)
	Sets the address sent by an instruction frame (QSPI_IAR.ADDR).
void	QSPI_SetInstructionCode (uint8_t instruction, uint8_t option)
	Sets the instruction and option codes (QSPI_ICR).
QSPI_HWREG_STATUS	QSPI_SetInstructionFrame (const QSPI_INSTRUCTION_FRAME *frame)
	Configures and launches an instruction frame (QSPI_IFR).
uint32_t	QSPI_SyncInstructionFrame (void)
	Synchronizes APB and AHB accesses after launching a data frame.
volatile uint8_t *	QSPI_GetMemoryPointer (uint32_t offset)
	Gets a pointer into the memory-mapped QSPI window.
bool	QSPI_SetDummyCycles (uint8_t dummy_cycles)
	Sets the number of dummy cycles of an instruction frame (QSPI_IFR.NBDUM).
void	QSPI_SetContinuousRead (bool is_enabled)
	Enables or disables continuous read mode (QSPI_IFR.CRM).
void	QSPI_SetScrambling (bool is_enabled)
	Enables or disables the scrambling function (QSPI_SMR.SCREN).
void	QSPI_SetScramblingRandomValueDisable (bool is_disabled)
	Enables or disables the scrambling random value (QSPI_SMR.RVDIS).
void	QSPI_SetScramblingKey (uint32_t key)
	Sets the user scrambling key (QSPI_SKR.USRK).
void	QSPI_EnableInterrupt (QSPI_INTERRUPT_SOURCE source)
	Enables the specified QSPI interrupt sources (QSPI_IER).
void	QSPI_DisableInterrupt (QSPI_INTERRUPT_SOURCE source)
	Disables the specified QSPI interrupt sources (QSPI_IDR).
QSPI_INTERRUPT_SOURCE	QSPI_GetInterruptMask (void)
	Gets the set of enabled interrupt sources (QSPI_IMR).
QSPI_STATUS_FLAG	QSPI_GetStatus (void)
	Reads the status register, preserving the read-to-clear flags.
bool	QSPI_StatusFlagIsSet (QSPI_STATUS_FLAG flag)
	Checks whether the specified status flags are set.
void	QSPI_ClearStatus (QSPI_STATUS_FLAG flag)
	Discards latched read-to-clear status flags.
QSPI_ERROR	QSPI_GetError (void)
	Gets the current QSPI error state.
void	QSPI_SetCallbackHandler (QSPI_CALLBACK callback)
	Registers a callback for QSPI interrupts.
void	QSPI_EnableWriteProtection (void)
	Enables write protection of the QSPI configuration registers.
void	QSPI_DisableWriteProtection (void)
	Disables write protection of the QSPI configuration registers.
bool	QSPI_WriteProtectionIsEnabled (void)
	Checks whether write protection is enabled (QSPI_WPMR.WPEN).
bool	QSPI_WriteProtectedIsViolated (void)
	Checks whether a write protection violation has occurred (QSPI_WPSR.WPVS).
uint8_t	QSPI_GetViolationSourceRegOffset (void)
	Gets the register offset that caused the write protection violation (QSPI_WPSR.WPVSRC).

Variables
uint8_t	QSPI_INSTRUCTION_FRAME::instruction
uint8_t	QSPI_INSTRUCTION_FRAME::option
uint8_t	QSPI_INSTRUCTION_FRAME::dummy_cycles
QSPI_LANE_WIDTH	QSPI_INSTRUCTION_FRAME::width
QSPI_ADDRESS_LENGTH	QSPI_INSTRUCTION_FRAME::address_length
QSPI_OPTION_LENGTH	QSPI_INSTRUCTION_FRAME::option_length
QSPI_TRANSFER_TYPE	QSPI_INSTRUCTION_FRAME::transfer_type
bool	QSPI_INSTRUCTION_FRAME::is_instruction_enabled
bool	QSPI_INSTRUCTION_FRAME::is_address_enabled
bool	QSPI_INSTRUCTION_FRAME::is_option_enabled
bool	QSPI_INSTRUCTION_FRAME::is_data_enabled
bool	QSPI_INSTRUCTION_FRAME::is_continuous_read_enabled

Description

Driver API for QSPI (plib_qspi.h)

Usage Example

The following example demonstrates typical usage of the QSPI peripheral:

/*******************************************************************************
* Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software
* and any derivatives exclusively with Microchip products. It is your
* responsibility to comply with third party license terms applicable to your
* use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
* PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN
* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*******************************************************************************/
 
/*******************************************************************************
 * @file configure_qspi.c
 * @brief Reference configuration for the QSPI on PIC32CZ-CA70 / MC70.
 * @details Template, not part of the PLIB. Copy it into the application and edit
 *          the values marked below. The PLIB itself applies no configuration
 *          policy: QSPI_ResetSoftware() only resets the peripheral, so choosing a
 *          clock rate, an operating mode and a pinout is the application's job,
 *          and this file shows one correct way to do it.
 *******************************************************************************/
 
#include "plib_qspi.h"
 
/* ---- Edit these to match the board and clock tree ------------------------ */
 
#define QSPI_PERIPHERAL_CLOCK_FREQUENCY   (150000000U)
 
#define QSPI_TARGET_BUS_SPEED             (30000000U)
 
#define QSPI_FLASH_DUMMY_CYCLES           (6U)
 
/* ---- Fixed by the device -------------------------------------------------- */
 
#define QSPI_PERIPHERAL_ID                (43U)
 
#define QSPI_PIOA_PIN_MASK                                                     \
    (((uint32_t)1U << 11) | ((uint32_t)1U << 12) | ((uint32_t)1U << 13) |      \
     ((uint32_t)1U << 14) | ((uint32_t)1U << 17))
 
#define QSPI_PIOD_PIN_MASK                ((uint32_t)1U << 31)
 
static void configureQspiPins(void)
{
    PIOA_REGS->PIO_ABCDSR[0] &= ~QSPI_PIOA_PIN_MASK;
    PIOA_REGS->PIO_ABCDSR[1] &= ~QSPI_PIOA_PIN_MASK;
    PIOA_REGS->PIO_PDR = QSPI_PIOA_PIN_MASK;
 
    PIOD_REGS->PIO_ABCDSR[0] &= ~QSPI_PIOD_PIN_MASK;
    PIOD_REGS->PIO_ABCDSR[1] &= ~QSPI_PIOD_PIN_MASK;
    PIOD_REGS->PIO_PDR = QSPI_PIOD_PIN_MASK;
}
 
static void enableQspiPeripheralClock(void)
{
    PMC_REGS->PMC_PCER1 = ((uint32_t)1U << (QSPI_PERIPHERAL_ID - 32U));
}
 
void QSPI_ConfigureSerialMemoryMode(void)
{
    enableQspiPeripheralClock();
    configureQspiPins();
 
    QSPI_ResetSoftware();
 
    if (QSPI_SetBusSpeed(QSPI_TARGET_BUS_SPEED,
                         QSPI_PERIPHERAL_CLOCK_FREQUENCY) != QSPI_HWREG_OK) {
        /* The requested rate is not reachable from this peripheral clock. The
         * peripheral keeps its reset divider; handle it however the application
         * requires. */
    }
 
    QSPI_SetClockPolarity(QSPI_CLOCK_POLARITY_IDLE_LOW);
    QSPI_SetClockPhase(QSPI_CLOCK_PHASE_CAPTURE_LEADING);
    QSPI_SetDelayBeforeSck(0U);
    QSPI_SetDelayBetweenChipSelects(0U);
 
    QSPI_SetOperatingMode(QSPI_OPERATING_MODE_MEMORY);
 
    QSPI_Enable();
}
 
void QSPI_ConfigureSpiMode(void)
{
    enableQspiPeripheralClock();
    configureQspiPins();
 
    QSPI_ResetSoftware();
 
    if (QSPI_SetBusSpeed(QSPI_TARGET_BUS_SPEED,
                         QSPI_PERIPHERAL_CLOCK_FREQUENCY) != QSPI_HWREG_OK) {
        /* See QSPI_ConfigureSerialMemoryMode(). */
    }
 
    QSPI_SetOperatingMode(QSPI_OPERATING_MODE_SPI);
    QSPI_SetTransferSize(QSPI_TRANSFER_SIZE_8BIT);
    QSPI_SetChipSelectMode(QSPI_CHIP_SELECT_MODE_LASTXFER);
    QSPI_SetClockPolarity(QSPI_CLOCK_POLARITY_IDLE_LOW);
    QSPI_SetClockPhase(QSPI_CLOCK_PHASE_CAPTURE_LEADING);
    QSPI_SetDelayBeforeSck(0U);
    QSPI_SetDelayBetweenConsecutiveTransfers(0U);
    QSPI_SetDelayBetweenChipSelects(0U);
 
    QSPI_Enable();
}
 
void QSPI_BuildQuadFastReadFrame(QSPI_INSTRUCTION_FRAME *frame)
{
    if (frame != NULL) {
        frame->instruction                = 0xEBU;  /* Fast Read Quad I/O */
        frame->option                     = 0U;
        frame->dummy_cycles               = QSPI_FLASH_DUMMY_CYCLES;
        frame->width                      = QSPI_LANE_WIDTH_QUAD_IO;
        frame->address_length             = QSPI_ADDRESS_LENGTH_24BIT;
        frame->option_length              = QSPI_OPTION_LENGTH_4BIT;
        frame->transfer_type              = QSPI_TRANSFER_TYPE_READ_MEMORY;
        frame->is_instruction_enabled     = true;
        frame->is_address_enabled         = true;
        frame->is_option_enabled          = false;
        frame->is_data_enabled            = true;
        frame->is_continuous_read_enabled = false;
    }
}

Macro Definition Documentation

QSPI_BAUD_MAX

#define QSPI_BAUD_MAX   (QSPI_SCR_SCBR_Msk >> QSPI_SCR_SCBR_Pos)

Maximum value of the serial clock baud rate divider (QSPI_SCR.SCBR).

QSPI_DELAY_MAX

#define QSPI_DELAY_MAX   (QSPI_MR_DLYBCT_Msk >> QSPI_MR_DLYBCT_Pos)

Maximum value of any of the QSPI delay fields (DLYBS, DLYBCT, DLYCS).

QSPI_DUMMY_CYCLES_MAX

#define QSPI_DUMMY_CYCLES_MAX   (QSPI_IFR_NBDUM_Msk >> QSPI_IFR_NBDUM_Pos)

Maximum number of dummy cycles (QSPI_IFR.NBDUM).

QSPI_ERROR_NONE

#define QSPI_ERROR_NONE   (0x00U)

No error

QSPI_ERROR_OVERRUN

#define QSPI_ERROR_OVERRUN   (0x01U)

QSPI_RDR was not read before new data came

QSPI_INTERRUPT_ALL

#define QSPI_INTERRUPT_ALL   (QSPI_IER_Msk)

All seven sources

QSPI_INTERRUPT_CSR

#define QSPI_INTERRUPT_CSR   (QSPI_IER_CSR_Msk)

Chip select rise

QSPI_INTERRUPT_CSS

#define QSPI_INTERRUPT_CSS   (QSPI_IER_CSS_Msk)

Chip select status change

QSPI_INTERRUPT_INSTRE

#define QSPI_INTERRUPT_INSTRE   (QSPI_IER_INSTRE_Msk)

Instruction end

QSPI_INTERRUPT_NONE

#define QSPI_INTERRUPT_NONE   (0x00000000U)

No source

QSPI_INTERRUPT_OVRES

#define QSPI_INTERRUPT_OVRES   (QSPI_IER_OVRES_Msk)

Overrun error

QSPI_INTERRUPT_RDRF

#define QSPI_INTERRUPT_RDRF   (QSPI_IER_RDRF_Msk)

Receive data register full

QSPI_INTERRUPT_TDRE

#define QSPI_INTERRUPT_TDRE   (QSPI_IER_TDRE_Msk)

Transmit data register empty

QSPI_INTERRUPT_TXEMPTY

#define QSPI_INTERRUPT_TXEMPTY   (QSPI_IER_TXEMPTY_Msk)

Transmission registers empty

QSPI_MEMORY_BASE_ADDRESS

#define QSPI_MEMORY_BASE_ADDRESS   (QSPIMEM_ADDR)

Base address of the memory-mapped QSPI window (QSPIMEM).

QSPI_MEMORY_SIZE

#define QSPI_MEMORY_SIZE   (QSPIMEM_SIZE)

Size of the memory-mapped QSPI window in bytes.

QSPI_STATUS_FLAG_ALL

#define QSPI_STATUS_FLAG_ALL   (QSPI_SR_Msk)

All eight flags

QSPI_STATUS_FLAG_CSR

#define QSPI_STATUS_FLAG_CSR   (QSPI_SR_CSR_Msk)

CS rise; cleared on read

QSPI_STATUS_FLAG_CSS

#define QSPI_STATUS_FLAG_CSS   (QSPI_SR_CSS_Msk)

Live CS state; 0 = asserted

QSPI_STATUS_FLAG_INSTRE

#define QSPI_STATUS_FLAG_INSTRE   (QSPI_SR_INSTRE_Msk)

Instr. end; cleared on read

QSPI_STATUS_FLAG_NONE

#define QSPI_STATUS_FLAG_NONE   (0x00000000U)

No flag set

QSPI_STATUS_FLAG_OVRES

#define QSPI_STATUS_FLAG_OVRES   (QSPI_SR_OVRES_Msk)

Overrun; cleared on read

QSPI_STATUS_FLAG_QSPIENS

#define QSPI_STATUS_FLAG_QSPIENS   (QSPI_SR_QSPIENS_Msk)

Live enable state

QSPI_STATUS_FLAG_RDRF

#define QSPI_STATUS_FLAG_RDRF   (QSPI_SR_RDRF_Msk)

Cleared by reading QSPI_RDR

QSPI_STATUS_FLAG_READ_TO_CLEAR

#define QSPI_STATUS_FLAG_READ_TO_CLEAR    (QSPI_SR_OVRES_Msk | QSPI_SR_CSR_Msk | QSPI_SR_INSTRE_Msk)

The subset of QSPI_SR flags that are cleared by reading the register.

A single read of QSPI_SR clears all three at once, so any code that polls one of them would destroy the other two. QSPI_GetStatus() latches these bits so that no event is lost; use QSPI_ClearStatus() to discard a latched bit.

QSPI_STATUS_FLAG_TDRE

#define QSPI_STATUS_FLAG_TDRE   (QSPI_SR_TDRE_Msk)

Cleared by writing QSPI_TDR

QSPI_STATUS_FLAG_TXEMPTY

#define QSPI_STATUS_FLAG_TXEMPTY   (QSPI_SR_TXEMPTY_Msk)

Cleared by writing QSPI_TDR

QSPI_WPMR_UNLOCK_KEY

#define QSPI_WPMR_UNLOCK_KEY   (QSPI_WPMR_WPKEY_PASSWD_Val)

Password that must accompany a write to QSPI_WPMR.WPEN.

Typedef Documentation

QSPI_CALLBACK

typedef void(* QSPI_CALLBACK) (QSPI_STATUS_FLAG status)

QSPI callback function type.

Invoked from QSPI_Handler, that is from interrupt context.

Delivery consumes the event: the read-to-clear flags reported here are dropped from the internal latch, so each interrupt reports only what is new. A polling caller must therefore not expect to see an event that the ISR has already delivered to a callback.

Parameters

status

Flags that caused this interrupt: the asserted QSPI_SR flags masked by the sources enabled in QSPI_IMR. Always non-zero.

QSPI_ERROR

typedef uint32_t QSPI_ERROR

QSPI error status bitmask type.

Defined as uint32_t so values can be OR'd together using bitwise operators without violating MISRA Rule 10.1 (enum essential type restriction).

Overrun is the only error the QSPI reports. A write protection violation is reported separately through QSPI_WriteProtectedIsViolated().

QSPI_INTERRUPT_SOURCE

typedef uint32_t QSPI_INTERRUPT_SOURCE

QSPI interrupt source bitmask type.

Defined as uint32_t so values can be OR'd together using bitwise operators without violating MISRA Rule 10.1 (enum essential type restriction).

QSPI_SR.QSPIENS is deliberately absent: it is a status-only bit and has no counterpart in QSPI_IER, QSPI_IDR or QSPI_IMR.

QSPI_STATUS_FLAG

typedef uint32_t QSPI_STATUS_FLAG

QSPI status flag bitmask type (QSPI_SR).

Defined as uint32_t so values can be OR'd together using bitwise operators without violating MISRA Rule 10.1 (enum essential type restriction).

Enumeration Type Documentation

QSPI_ADDRESS_LENGTH

enum QSPI_ADDRESS_LENGTH

Length of the address phase of an instruction frame (QSPI_IFR.ADDRL).

Enumerator
QSPI_ADDRESS_LENGTH_24BIT	24-bit address
QSPI_ADDRESS_LENGTH_32BIT	32-bit address

QSPI_CHIP_SELECT_MODE

enum QSPI_CHIP_SELECT_MODE

Chip select behaviour at the end of a transfer (QSPI_MR.CSMODE).

Enumerator
QSPI_CHIP_SELECT_MODE_NOT_RELOADED	Deasserted if QSPI_TDR.TD was not reloaded before the transfer ended
QSPI_CHIP_SELECT_MODE_LASTXFER	Deasserted when QSPI_CR.LASTXFER is written and the character has gone
QSPI_CHIP_SELECT_MODE_SYSTEMATICALLY	Deasserted systematically after every transfer

QSPI_CLOCK_PHASE

enum QSPI_CLOCK_PHASE

QSCK edge on which data is captured (QSPI_SCR.CPHA).

Enumerator
QSPI_CLOCK_PHASE_CAPTURE_LEADING	Data captured on the leading edge, changed on the following edge
QSPI_CLOCK_PHASE_CAPTURE_TRAILING	Data changed on the leading edge, captured on the following edge

QSPI_CLOCK_POLARITY

enum QSPI_CLOCK_POLARITY

Inactive state of QSCK (QSPI_SCR.CPOL).

Enumerator
QSPI_CLOCK_POLARITY_IDLE_LOW	QSCK is low when inactive
QSPI_CLOCK_POLARITY_IDLE_HIGH	QSCK is high when inactive

QSPI_HWREG_STATUS

enum QSPI_HWREG_STATUS

Result of a QSPI hardware register operation.

Shared shape with the sibling serial PLIBs. The QSPI implementation only ever returns QSPI_HWREG_OK or QSPI_HWREG_INVALID_PARAM - it has no blocking path, so QSPI_HWREG_TIMEOUT and QSPI_HWREG_BUSY cannot occur.

Enumerator
QSPI_HWREG_OK	Operation applied successfully
QSPI_HWREG_ERROR	Unspecified failure
QSPI_HWREG_INVALID_PARAM	A parameter was out of range or NULL
QSPI_HWREG_TIMEOUT	Reserved; never returned by this PLIB
QSPI_HWREG_BUSY	Reserved; never returned by this PLIB
QSPI_HWREG_UNSUPPORTED	Feature not implemented on this device

QSPI_LANE_WIDTH

enum QSPI_LANE_WIDTH

Number of data lanes used by each phase of an instruction frame (QSPI_IFR.WIDTH).

Read as instruction / address-option / data.

Enumerator
QSPI_LANE_WIDTH_SINGLE_BIT_SPI	Single / single / single
QSPI_LANE_WIDTH_DUAL_OUTPUT	Single / single / dual
QSPI_LANE_WIDTH_QUAD_OUTPUT	Single / single / quad
QSPI_LANE_WIDTH_DUAL_IO	Single / dual / dual
QSPI_LANE_WIDTH_QUAD_IO	Single / quad / quad
QSPI_LANE_WIDTH_DUAL_CMD	Dual / dual / dual
QSPI_LANE_WIDTH_QUAD_CMD	Quad / quad / quad

QSPI_OPERATING_MODE

enum QSPI_OPERATING_MODE

QSPI operating mode (QSPI_MR.SMM).

Writing QSPI_OPERATING_MODE_MEMORY forces QSPI_MR.CSMODE to QSPI_CHIP_SELECT_MODE_LASTXFER, and QSPI_MR.DLYBCT must then be zero.

Enumerator
QSPI_OPERATING_MODE_SPI	SPI mode
QSPI_OPERATING_MODE_MEMORY	Serial Memory mode

QSPI_OPTION_LENGTH

enum QSPI_OPTION_LENGTH

Length of the option phase of an instruction frame (QSPI_IFR.OPTL).

The option code cannot be shorter than the number of lanes carrying it, so the legal values depend on QSPI_LANE_WIDTH. See QSPI_SetInstructionFrame().

Enumerator
QSPI_OPTION_LENGTH_1BIT	1 bit long
QSPI_OPTION_LENGTH_2BIT	2 bits long
QSPI_OPTION_LENGTH_4BIT	4 bits long
QSPI_OPTION_LENGTH_8BIT	8 bits long

QSPI_TRANSFER_SIZE

enum QSPI_TRANSFER_SIZE

Number of bits per transfer in SPI mode (QSPI_MR.NBBITS).

The field is 4 bits wide and encodes 8 through 16 bits per character. Only the two endpoints carry symbolic names in the device header; the intermediate values are equally valid.

Enumerator
QSPI_TRANSFER_SIZE_8BIT	8 bits per transfer
QSPI_TRANSFER_SIZE_9BIT	9 bits per transfer
QSPI_TRANSFER_SIZE_10BIT	10 bits per transfer
QSPI_TRANSFER_SIZE_11BIT	11 bits per transfer
QSPI_TRANSFER_SIZE_12BIT	12 bits per transfer
QSPI_TRANSFER_SIZE_13BIT	13 bits per transfer
QSPI_TRANSFER_SIZE_14BIT	14 bits per transfer
QSPI_TRANSFER_SIZE_15BIT	15 bits per transfer
QSPI_TRANSFER_SIZE_16BIT	16 bits per transfer

QSPI_TRANSFER_TYPE

enum QSPI_TRANSFER_TYPE

Kind of data transfer performed by an instruction frame (QSPI_IFR.TFRTYP).

The _MEMORY variants address actual memory contents: scrambling is applied when enabled, and a read at a random location (a fetch) is possible. The other two address the memory's own registers: scrambling is never applied and random-location reads are not possible.

Enumerator
QSPI_TRANSFER_TYPE_READ	Read from the serial memory, but not memory data (for example a status register)
QSPI_TRANSFER_TYPE_READ_MEMORY	Read memory data - fetch or execute-in-place
QSPI_TRANSFER_TYPE_WRITE	Write to the serial memory, but not memory data (for example a config register)
QSPI_TRANSFER_TYPE_WRITE_MEMORY	Program memory data

Function Documentation

QSPI_ClearStatus()

void QSPI_ClearStatus

(

QSPI_STATUS_FLAG

flag

)

Discards latched read-to-clear status flags.

Clears the named flags from the internal latch so a later QSPI_GetStatus() no longer reports them. Flags outside QSPI_STATUS_FLAG_READ_TO_CLEAR are ignored: the hardware owns them and they cannot be cleared this way.

Parameters

flag	One or more QSPI_STATUS_FLAG values, OR'd together.

Returns

None

QSPI_Disable()

void QSPI_Disable

(

void

)

Disables the QSPI (QSPI_CR.QSPIDIS).

Returns

None

QSPI_DisableInterrupt()

void QSPI_DisableInterrupt

(

QSPI_INTERRUPT_SOURCE

source

)

Disables the specified QSPI interrupt sources (QSPI_IDR).

QSPI_IDR is write-only and clear-only, so sources not named in source are left untouched.

Parameters

source

One or more QSPI_INTERRUPT_SOURCE values, OR'd together.

Returns

None

QSPI_DisableWriteProtection()

void QSPI_DisableWriteProtection

(

void

)

Disables write protection of the QSPI configuration registers.

Clears QSPI_WPMR.WPEN with the required key.

Returns

None

QSPI_Enable()

void QSPI_Enable

(

void

)

Enables the QSPI (QSPI_CR.QSPIEN).

Enabling sets QSPI_SR.TDRE, which reads as zero while the peripheral is disabled.

Returns

None

QSPI_EnableInterrupt()

void QSPI_EnableInterrupt

(

QSPI_INTERRUPT_SOURCE

source

)

Enables the specified QSPI interrupt sources (QSPI_IER).

QSPI_IER is write-only and set-only, so sources not named in source are left untouched. Enabling a source here does not enable the QSPI interrupt in the NVIC.

Parameters

source

One or more QSPI_INTERRUPT_SOURCE values, OR'd together.

Returns

None

QSPI_SetCallbackHandler(qspiEventHandler);
QSPI_EnableInterrupt(QSPI_INTERRUPT_INSTRE | QSPI_INTERRUPT_OVRES);
NVIC_EnableIRQ(QSPI_IRQn);

QSPI_EnableWriteProtection()

void QSPI_EnableWriteProtection

(

void

)

Enables write protection of the QSPI configuration registers.

Sets QSPI_WPMR.WPEN with the required key. While enabled, writes to QSPI_MR, QSPI_SCR, QSPI_SMR and QSPI_SKR are discarded and recorded in QSPI_WPSR. QSPI_IFR, QSPI_IAR and QSPI_ICR are not protected, so instruction frames still work normally.

Returns

None

Note

Configure QSPI_MR, QSPI_SCR, QSPI_SMR and QSPI_SKR (mode, chip-select mode, transfer size, clock polarity/phase, bus speed, delays, scrambling) before enabling protection: once WPEN is set, writes to them are discarded and flagged in QSPI_WPSR. Use QSPI_DisableWriteProtection() to reconfigure.

QSPI_EndTransfer()

void QSPI_EndTransfer

(

void

)

Marks the current transfer as the last one (QSPI_CR.LASTXFER).

With QSPI_CHIP_SELECT_MODE_LASTXFER the chip select is deasserted once the character in QSPI_TDR has been sent. In Serial Memory mode this is the step that closes an instruction frame, and must be issued after all data has been moved through the memory window.

Returns

None

QSPI_GetBusSpeed()

uint32_t QSPI_GetBusSpeed

(

uint32_t

clk_frequency

)

Gets the serial clock baud rate currently configured.

Returns clk_frequency / (SCBR + 1) using the value held in QSPI_SCR.SCBR.

Parameters

clk_frequency

Peripheral clock frequency in Hz.

Returns

The achieved QSCK frequency in Hz, or zero if clk_frequency is zero.

QSPI_GetError()

QSPI_ERROR QSPI_GetError

(

void

)

Gets the current QSPI error state.

Overrun is the only error the peripheral reports. The overrun indication is consumed by this call, mirroring the read-to-clear behaviour of QSPI_SR.OVRES in hardware, so a second call reports QSPI_ERROR_NONE unless a new overrun has occurred.

Returns

QSPI_ERROR bitmask indicating the last error condition.

QSPI_GetInterruptMask()

QSPI_INTERRUPT_SOURCE QSPI_GetInterruptMask

(

void

)

Gets the set of enabled interrupt sources (QSPI_IMR).

Returns

Bitmask of currently enabled QSPI_INTERRUPT_SOURCE values.

QSPI_GetMemoryPointer()

volatile uint8_t * QSPI_GetMemoryPointer

(

uint32_t

offset

)

Gets a pointer into the memory-mapped QSPI window.

In Serial Memory mode all data moves through this window rather than through QSPI_TDR and QSPI_RDR. The returned pointer is volatile because each access drives a transfer on the serial bus.

Parameters

offset

Byte offset from QSPI_MEMORY_BASE_ADDRESS.

Returns

A pointer to that offset within the window, or NULL if offset is at or beyond QSPI_MEMORY_SIZE.

Note

With QSPI_TRANSFER_TYPE_READ_MEMORY or QSPI_TRANSFER_TYPE_WRITE_MEMORY, non-sequential accesses cause a new instruction to be sent automatically. With the other two transfer types the QSPI ignores the access address entirely, so any offset reaches the same data.

If a DMA controller is used to move the data, its accesses to this window must be 32-bit aligned. This PLIB exposes no DMA controls: the QSPI is an XDMAC request source and does not own a channel.

QSPI_GetStatus()

QSPI_STATUS_FLAG QSPI_GetStatus

(

void

)

Reads the status register, preserving the read-to-clear flags.

Performs exactly one read of QSPI_SR. That read clears OVRES, CSR and INSTRE in hardware, all three at once, so this function latches them internally before returning; a caller polling one flag therefore cannot destroy another. The remaining flags reflect the state at the moment of the read.

Returns

The status flags, combining this read with any previously latched read-to-clear flags.

Note

Called from both thread and interrupt context. The latch update is performed with interrupts masked so a QSPI interrupt arriving mid-update cannot lose a flag.

This function does not consume what it reports. Latched flags persist until dropped by QSPI_ClearStatus(), by QSPI_GetError() in the case of OVRES, or by delivery to a callback from QSPI_Handler. Because of that, calling this to perform the dummy QSPI_SR read that the datasheet places before QSPI_CR.LASTXFER is not on its own enough to make the following wait meaningful: follow it with QSPI_ClearStatus(QSPI_STATUS_FLAG_INSTRE | QSPI_STATUS_FLAG_CSR) so an instruction end left over from an earlier frame cannot satisfy the wait immediately.

QSPI_STATUS_FLAG_CSS is a live level with inverted sense: it reads zero while the chip select is asserted.

QSPI_GetViolationSourceRegOffset()

uint8_t QSPI_GetViolationSourceRegOffset

(

void

)

Gets the register offset that caused the write protection violation (QSPI_WPSR.WPVSRC).

Returns

Offset within the QSPI register map of the write that was discarded.

Note

Reading QSPI_WPSR clears the violation status.

QSPI_IsEnabled()

bool QSPI_IsEnabled

(

void

)

Checks whether the QSPI is enabled (QSPI_SR.QSPIENS).

Returns

true if enabled, false if disabled.

Note

Reads QSPI_SR through QSPI_GetStatus(), so any pending read-to-clear flags are latched rather than lost.

QSPI_Receive()

uint16_t QSPI_Receive

(

void

)

Reads one character from the receive holding register (QSPI_RDR.RD).

Reading QSPI_RDR clears QSPI_SR.RDRF. Check QSPI_RxIsReady() first; reading an empty QSPI_RDR returns the previous contents.

Returns

The received character, zero-extended to 16 bits.

Note

SPI mode only.

QSPI_ResetSoftware()

void QSPI_ResetSoftware

(

void

)

Performs a software reset of the QSPI (QSPI_CR.SWRST).

Equivalent to a power-on reset of the peripheral. Any transfer in progress is abandoned and the chip select is deasserted. Because the reset returns QSPI_SR to zero, the latched read-to-clear flags are discarded too - otherwise a stale INSTRE would make the next QSPI_StatusFlagIsSet() report an instruction end that belonged to the abandoned transfer.

Returns

None

QSPI_RxIsReady()

bool QSPI_RxIsReady

(

void

)

Checks whether QSPI_RDR holds an unread character (QSPI_SR.RDRF).

Returns

true if a character is waiting, false otherwise.

Note

Reads QSPI_SR through QSPI_GetStatus(), so any pending read-to-clear flags are latched rather than lost.

QSPI_Send()

void QSPI_Send

(

uint16_t

data

)

Writes one character to the transmit holding register (QSPI_TDR.TD).

Writing QSPI_TDR clears QSPI_SR.TDRE and QSPI_SR.TXEMPTY. Check QSPI_TxIsReady() before calling, otherwise the previous character is lost.

Parameters

data	Character to transmit. Bits above the configured transfer size are ignored by the hardware.

Returns

None

Note

SPI mode only. In Serial Memory mode data moves through the memory window returned by QSPI_GetMemoryPointer().

QSPI_SetBusSpeed()

QSPI_HWREG_STATUS QSPI_SetBusSpeed	(	uint32_t	bus_speed,
		uint32_t	clk_frequency )

Sets the serial clock baud rate (QSPI_SCR.SCBR).

Computes SCBR = (clk_frequency / bus_speed) - 1. Because the divider is an integer, the achieved rate is the nearest value at or above bus_speed that the divider can express; read it back with QSPI_GetBusSpeed().

Parameters

bus_speed	Desired QSCK frequency in Hz. Must be non-zero and no greater than clk_frequency.
clk_frequency	Peripheral clock frequency in Hz.

Returns

QSPI_HWREG_OK on success, or QSPI_HWREG_INVALID_PARAM if either argument is zero, if bus_speed exceeds clk_frequency, or if the required divider exceeds QSPI_BAUD_MAX.

Note

No register is written when QSPI_HWREG_INVALID_PARAM is returned.

QSPI_SCR is write-protected while QSPI_WPMR.WPEN is set.

A non-QSPI_HWREG_OK return means the requested rate is not reachable from the peripheral clock.

if (QSPI_SetBusSpeed(10000000U, 150000000U) != QSPI_HWREG_OK) {
    return;
}

QSPI_SetCallbackHandler()

void QSPI_SetCallbackHandler

(

QSPI_CALLBACK

callback

)

Registers a callback for QSPI interrupts.

The callback is invoked from QSPI_Handler, that is from interrupt context, with the status flags that were asserted. Keep it short and do not block in it. Only sources enabled through QSPI_EnableInterrupt() can cause it to run.

Parameters

callback

Pointer to the callback function. Pass NULL to unregister.

Returns

None

QSPI_SetChipSelectMode()

void QSPI_SetChipSelectMode

(

QSPI_CHIP_SELECT_MODE

mode

)

Sets the chip select mode (QSPI_MR.CSMODE).

Parameters

mode	Chip select behaviour at the end of a transfer.

Returns

None

Note

Has no lasting effect in Serial Memory mode, which forces the field to QSPI_CHIP_SELECT_MODE_LASTXFER. Call this after QSPI_SetOperatingMode(), not before.

QSPI_MR is write-protected while QSPI_WPMR.WPEN is set.

QSPI_SetClockPhase()

void QSPI_SetClockPhase

(

QSPI_CLOCK_PHASE

phase

)

Sets the QSCK edge on which data is captured (QSPI_SCR.CPHA).

Parameters

phase

Clock phase to apply.

Returns

None

Note

QSPI_SCR is write-protected while QSPI_WPMR.WPEN is set.

QSPI_SetClockPolarity()

void QSPI_SetClockPolarity

(

QSPI_CLOCK_POLARITY

polarity

)

Sets the inactive state of QSCK (QSPI_SCR.CPOL).

Parameters

polarity

Clock polarity to apply.

Returns

None

Note

QSPI_SCR is write-protected while QSPI_WPMR.WPEN is set.

QSPI_SetContinuousRead()

void QSPI_SetContinuousRead

(

bool

is_enabled

)

Enables or disables continuous read mode (QSPI_IFR.CRM).

Parameters

is_enabled

true to enable continuous read mode, false to disable.

Returns

None

Note

Continuous read mode requires QSPI_TRANSFER_TYPE_READ_MEMORY and a serial Flash memory that supports it. Enabled in any other combination, the data read out of the memory is unpredictable. QSPI_SetInstructionFrame() rejects the invalid combination; this function does not, because it cannot see the transfer type that will be in force, so the caller must guarantee QSPI_TRANSFER_TYPE_READ_MEMORY is the active transfer type before enabling.

Warning

This writes QSPI_IFR, and writing QSPI_IFR re-sends the instruction frame if the frame currently configured has no data phase. See QSPI_SetDummyCycles() for the same hazard and how to avoid it.

QSPI_SetDelayBeforeSck()

void QSPI_SetDelayBeforeSck

(

uint8_t

delay

)

Sets the delay before the first QSCK edge (QSPI_SCR.DLYBS).

The delay between chip select assertion and the first clock edge, in peripheral clock periods, equals delay. A value of zero gives half a QSCK period.

Parameters

delay

Field value, 0 to QSPI_DELAY_MAX.

Returns

None

Note

QSPI_SCR is write-protected while QSPI_WPMR.WPEN is set.

QSPI_SetDelayBetweenChipSelects()

void QSPI_SetDelayBetweenChipSelects

(

uint8_t

delay

)

Sets the minimum inactive chip select delay (QSPI_MR.DLYCS).

The delay in peripheral clock periods equals delay. A value of zero gives one peripheral clock period.

Parameters

delay

Field value, 0 to QSPI_DELAY_MAX.

Returns

None

Note

QSPI_MR is write-protected while QSPI_WPMR.WPEN is set.

QSPI_SetDelayBetweenConsecutiveTransfers()

void QSPI_SetDelayBetweenConsecutiveTransfers

(

uint8_t

delay

)

Sets the delay between consecutive transfers (QSPI_MR.DLYBCT).

The delay in peripheral clock periods is delay * 32. A value of zero means no delay is inserted.

Parameters

delay

Field value, 0 to QSPI_DELAY_MAX.

Returns

None

Note

In Serial Memory mode this delay is not programmable: the field is ignored and must be written to zero.

QSPI_MR is write-protected while QSPI_WPMR.WPEN is set.

QSPI_SetDummyCycles()

bool QSPI_SetDummyCycles

(

uint8_t

dummy_cycles

)

Sets the number of dummy cycles of an instruction frame (QSPI_IFR.NBDUM).

Provided for adjusting the dummy cycle count without rewriting the whole frame; QSPI_SetInstructionFrame() sets the field too.

Parameters

dummy_cycles

Number of dummy cycles, 0 to QSPI_DUMMY_CYCLES_MAX.

Returns

true if applied, false if dummy_cycles is out of range, in which case no register is written.

Warning

This writes QSPI_IFR, and writing QSPI_IFR re-sends the instruction frame if the frame currently configured has no data phase. Calling it after QSPI_SetInstructionFrame() has launched a data-less frame - an erase or a write-enable, say - issues that instruction a second time. Set the dummy cycle count before launching a frame, or set it as part of the frame through QSPI_SetInstructionFrame().

QSPI_SetInstructionAddress()

void QSPI_SetInstructionAddress

(

uint32_t

address

)

Sets the address sent by an instruction frame (QSPI_IAR.ADDR).

Call this before QSPI_SetInstructionFrame() whenever the frame has is_address_enabled set.

Parameters

address

Address to send to the serial memory.

Returns

None

QSPI_SetInstructionCode()

void QSPI_SetInstructionCode	(	uint8_t	instruction,
		uint8_t	option )

Sets the instruction and option codes (QSPI_ICR).

Call this before QSPI_SetInstructionFrame() whenever the frame has is_instruction_enabled or is_option_enabled set. Both fields are written together in a single register access.

Parameters

instruction	Instruction code (QSPI_ICR.INST).
option	Option code (QSPI_ICR.OPT). Pass zero when the frame has no option phase.

Returns

None

QSPI_SetInstructionFrame()

QSPI_HWREG_STATUS QSPI_SetInstructionFrame

(

const QSPI_INSTRUCTION_FRAME *

frame

)

Configures and launches an instruction frame (QSPI_IFR).

Composes frame into a single write to QSPI_IFR. If the frame has no data phase the write itself starts the transfer; if it has one, the transfer starts on the first access to the memory window, and QSPI_SyncInstructionFrame() must be called first.

All parameters are validated before any register is touched, so a rejected frame leaves the hardware untouched.

Parameters

frame

Frame description. Must not be NULL.

Returns

QSPI_HWREG_OK if the frame was written, otherwise QSPI_HWREG_INVALID_PARAM when

• frame is NULL, or
• dummy_cycles exceeds QSPI_DUMMY_CYCLES_MAX, or
• the option phase is enabled and option_length is shorter than the number of lanes width uses for it - a 1-bit option code cannot be sent over 4 lanes, or
• continuous read is enabled without QSPI_TRANSFER_TYPE_READ_MEMORY, which the hardware requires.

Note

QSPI_IFR is not covered by QSPI_WPMR write protection.

QSPI_INSTRUCTION_FRAME frame = { 0 };
 
frame.width                  = QSPI_LANE_WIDTH_QUAD_IO;
frame.address_length         = QSPI_ADDRESS_LENGTH_24BIT;
frame.transfer_type          = QSPI_TRANSFER_TYPE_READ_MEMORY;
frame.dummy_cycles           = 6U;
frame.is_instruction_enabled = true;
frame.is_address_enabled     = true;
frame.is_data_enabled        = true;
 
QSPI_SetInstructionAddress(0x000100U);
QSPI_SetInstructionCode(0xEBU, 0U);
if (QSPI_SetInstructionFrame(&frame) == QSPI_HWREG_OK) {
    (void)QSPI_SyncInstructionFrame();
}

QSPI_SetLoopback()

void QSPI_SetLoopback

(

bool

is_enabled

)

Enables or disables the local loopback path (QSPI_MR.LLB).

With loopback enabled, QIO0 is internally connected to QIO1 so transmitted data is received back without leaving the device. Intended for self-test.

Parameters

is_enabled

true to enable loopback, false to disable it.

Returns

None

Note

QSPI_MR is write-protected while QSPI_WPMR.WPEN is set.

QSPI_SetOperatingMode()

void QSPI_SetOperatingMode

(

QSPI_OPERATING_MODE

mode

)

Selects SPI mode or Serial Memory mode (QSPI_MR.SMM).

Parameters

mode	Operating mode to apply.

Returns

None

Note

Writing QSPI_OPERATING_MODE_MEMORY forces QSPI_MR.CSMODE to QSPI_CHIP_SELECT_MODE_LASTXFER, so a chip select mode set beforehand is discarded. In this mode QSPI_MR.DLYBCT is ignored and must be zero.

QSPI_MR is write-protected while QSPI_WPMR.WPEN is set.

QSPI_SetScrambling()

void QSPI_SetScrambling

(

bool

is_enabled

)

Enables or disables the scrambling function (QSPI_SMR.SCREN).

Scrambling is applied only to frames using QSPI_TRANSFER_TYPE_READ_MEMORY or QSPI_TRANSFER_TYPE_WRITE_MEMORY.

Parameters

is_enabled

true to enable scrambling and unscrambling.

Returns

None

Note

QSPI_SMR is write-protected while QSPI_WPMR.WPEN is set.

Set the key with QSPI_SetScramblingKey() before enabling. Data written with one key cannot be read back with another.

QSPI_SetScramblingKey()

void QSPI_SetScramblingKey

(

uint32_t

key

)

Sets the user scrambling key (QSPI_SKR.USRK).

Parameters

key	Scrambling key.

Returns

None

Note

QSPI_SKR is write-protected while QSPI_WPMR.WPEN is set.

QSPI_SKR is write-only; the key cannot be read back.

QSPI_SetScramblingRandomValueDisable()

void QSPI_SetScramblingRandomValueDisable

(

bool

is_disabled

)

Enables or disables the scrambling random value (QSPI_SMR.RVDIS).

Parameters

is_disabled

true to disable the random value, false to allow it.

Returns

None

Note

QSPI_SMR is write-protected while QSPI_WPMR.WPEN is set.

QSPI_SetTransferSize()

void QSPI_SetTransferSize

(

QSPI_TRANSFER_SIZE

size

)

Sets the number of bits per transfer in SPI mode (QSPI_MR.NBBITS).

Parameters

size	Character length, 8 to 16 bits.

Returns

None

Note

Applies to SPI mode only; Serial Memory mode always transfers bytes.

QSPI_MR is write-protected while QSPI_WPMR.WPEN is set.

QSPI_StatusFlagIsSet()

bool QSPI_StatusFlagIsSet

(

QSPI_STATUS_FLAG

flag

)

Checks whether the specified status flags are set.

Reads the status through QSPI_GetStatus(), so read-to-clear flags are latched rather than consumed and this function is safe to call in a polling loop.

Parameters

flag	One or more QSPI_STATUS_FLAG values, OR'd together.

Returns

true if any of the flags in flag is set.

QSPI_EndTransfer();
while (!QSPI_StatusFlagIsSet(QSPI_STATUS_FLAG_INSTRE)) {
}
QSPI_ClearStatus(QSPI_STATUS_FLAG_INSTRE);

QSPI_SyncInstructionFrame()

uint32_t QSPI_SyncInstructionFrame

(

void

)

Synchronizes APB and AHB accesses after launching a data frame.

Performs the read of QSPI_IFR that the hardware requires between the write that configures a frame with a data phase and the first access to the memory window. Skipping it leaves the two buses unsynchronized and the first data access unreliable.

The register value is returned rather than discarded so the read cannot be optimized away, which also makes this the QSPI_IFR getter.

Returns

The current contents of QSPI_IFR.

(void)QSPI_SetInstructionFrame(&frame);
(void)QSPI_SyncInstructionFrame();

QSPI_TransferIsComplete()

bool QSPI_TransferIsComplete

(

void

)

Checks whether all requested transfers have completed (QSPI_SR.TXEMPTY).

Returns

true if the transmit shift register and QSPI_TDR are both empty.

Note

Reads QSPI_SR through QSPI_GetStatus(), so any pending read-to-clear flags are latched rather than lost.

QSPI_TxIsReady()

bool QSPI_TxIsReady

(

void

)

Checks whether QSPI_TDR can accept a character (QSPI_SR.TDRE).

Returns

true if QSPI_TDR is empty, false if a character is still pending.

Note

Reads QSPI_SR through QSPI_GetStatus(), so any pending read-to-clear flags are latched rather than lost.

QSPI_WriteProtectedIsViolated()

bool QSPI_WriteProtectedIsViolated

(

void

)

Checks whether a write protection violation has occurred (QSPI_WPSR.WPVS).

Returns

true if a protected register was written while protection was on.

Note

Reading QSPI_WPSR clears the violation status, so this reports each violation once. Call QSPI_GetViolationSourceRegOffset() first if the offending register offset is needed.

QSPI_WriteProtectionIsEnabled()

bool QSPI_WriteProtectionIsEnabled

(

void

)

Checks whether write protection is enabled (QSPI_WPMR.WPEN).

Returns

true if write protection is enabled.

Variable Documentation

address_length

QSPI_ADDRESS_LENGTH QSPI_INSTRUCTION_FRAME::address_length

Length of the address phase

dummy_cycles

uint8_t QSPI_INSTRUCTION_FRAME::dummy_cycles

Dummy cycles between address and data, 0 to QSPI_DUMMY_CYCLES_MAX

instruction

uint8_t QSPI_INSTRUCTION_FRAME::instruction

Instruction code sent when is_instruction_enabled is true (QSPI_ICR.INST)

is_address_enabled

bool QSPI_INSTRUCTION_FRAME::is_address_enabled

Send the address held in QSPI_IAR

is_continuous_read_enabled

bool QSPI_INSTRUCTION_FRAME::is_continuous_read_enabled

Enable continuous read mode; requires QSPI_TRANSFER_TYPE_READ_MEMORY

is_data_enabled

bool QSPI_INSTRUCTION_FRAME::is_data_enabled

The frame has a data phase, moved through the memory-mapped window

is_instruction_enabled

bool QSPI_INSTRUCTION_FRAME::is_instruction_enabled

Send the instruction code

is_option_enabled

bool QSPI_INSTRUCTION_FRAME::is_option_enabled

Send the option code

option

uint8_t QSPI_INSTRUCTION_FRAME::option

Option code sent when is_option_enabled is true (QSPI_ICR.OPT)

option_length

QSPI_OPTION_LENGTH QSPI_INSTRUCTION_FRAME::option_length

Length of the option phase; must be consistent with width

transfer_type

QSPI_TRANSFER_TYPE QSPI_INSTRUCTION_FRAME::transfer_type

Whether the frame reads or writes, and whether it targets memory data

width

QSPI_LANE_WIDTH QSPI_INSTRUCTION_FRAME::width

Number of lanes used by each phase of the frame