SPI Interface

Driver API for SPI (plib_spi0.h) More...

Macros
#define	SPI_BAUD_MAX   (0xFFU)
	Maximum value for the SPI baud rate register (SCBR field).

Typedefs
typedef void(*	SPI_CALLBACK) (uint32_t intr)
	Callback function type for SPI interrupts.

Enumerations
enum	SPI_HWREG_STATUS {   SPI_HWREG_OK = 0 , SPI_HWREG_ERROR , SPI_HWREG_INVALID_PARAM , SPI_HWREG_TIMEOUT ,   SPI_HWREG_BUSY , SPI_HWREG_UNSUPPORTED }
	Status codes for SPI hardware register operations. More...
enum	SPI_OPERATING_MODE { SPI_CLIENT_MODE = 0U , SPI_HOST_MODE = 1U }
	SPI operating modes. More...
enum	SPI_PERIPHERAL_SELECT_MODE { SPI_FIXED_PERIPHERAL_SELECT = 0U , SPI_VARIABLE_PERIPHERAL_SELECT = 1U }
	Peripheral select mode: fixed or variable per transfer. More...
enum	SPI_PCS_DECODE { SPI_CHIP_SELECT_DIRECT = 0U , SPI_CHIP_SELECT_DECODE = 1U }
	Chip select decoding mode: direct NPCS pins or external decoder. More...
enum	SPI_MODE_FAULT { SPI_MODE_FAULT_ENABLE = 0U , SPI_MODE_FAULT_DISABLE = 1U }
	Mode fault detection: enable to detect host conflicts. More...
enum	SPI_TRANSFERFLOW_MODE { SPI_TRANSFER_FLOW_NORMAL = 0U , SPI_TRANSFER_FLOW_WAIT_FOR_READ = 1U }
	Transfer flow control: continuous or wait-for-read. More...
enum	SPI_LOOPBACK { SPI_LOOPBACK_DISABLE = 0U , SPI_LOOPBACK_ENABLE = 1U }
	Internal loopback mode: disabled for normal operation, enabled for self-test. More...
enum	SPI_TRANSFER_SIZE {   SPI_TRANSFER_SIZE_8BIT = 0U , SPI_TRANSFER_SIZE_9BIT = 1U , SPI_TRANSFER_SIZE_10BIT = 2U , SPI_TRANSFER_SIZE_11BIT = 3U ,   SPI_TRANSFER_SIZE_12BIT = 4U , SPI_TRANSFER_SIZE_13BIT = 5U , SPI_TRANSFER_SIZE_14BIT = 6U , SPI_TRANSFER_SIZE_15BIT = 7U ,   SPI_TRANSFER_SIZE_16BIT = 8U }
	SPI character/transfer size options. More...
enum	SPI_INTERRUPT_SOURCE {   SPI_INTERRUPT_NONE = 0U , SPI_INTERRUPT_RDRF = (1U << SPI_IER_RDRF_Pos) , SPI_INTERRUPT_TDRE = (1U << SPI_IER_TDRE_Pos) , SPI_INTERRUPT_MODF = (1U << SPI_IER_MODF_Pos) ,   SPI_INTERRUPT_OVRES = (1U << SPI_IER_OVRES_Pos) , SPI_INTERRUPT_NSSR = (1U << SPI_IER_NSSR_Pos) , SPI_INTERRUPT_TXEMPTY = (1U << SPI_IER_TXEMPTY_Pos) , SPI_INTERRUPT_UNDES = (1U << SPI_IER_UNDES_Pos) ,   SPI_INTERRUPT_ALL }
	SPI interrupt sources. More...
enum	SPI_INTERRUPT_FLAG {   SPI_FLAG_RDRF = (1U << SPI_SR_RDRF_Pos) , SPI_FLAG_TDRE = (1U << SPI_SR_TDRE_Pos) , SPI_FLAG_MODF = (1U << SPI_SR_MODF_Pos) , SPI_FLAG_OVRES = (1U << SPI_SR_OVRES_Pos) ,   SPI_FLAG_NSSR = (1U << SPI_SR_NSSR_Pos) , SPI_FLAG_TXEMPTY = (1U << SPI_SR_TXEMPTY_Pos) , SPI_FLAG_UNDES = (1U << SPI_SR_UNDES_Pos) , SPI_FLAG_ALL }
	SPI interrupt flags. More...

Functions
void	SPI0_Enable (void)
	Enable the SPI module.
void	SPI0_Disable (void)
	Disable the SPI module.
void	SPI0_Send (uint16_t data)
	Send a single data word via SPI.
uint16_t	SPI0_Receive (void)
	Receive a single data word via SPI.
bool	SPI0_RxIsReady (void)
	Check if SPI receiver is ready.
bool	SPI0_TxIsReady (void)
	Check if SPI transmitter is ready.
bool	SPI0_TransferIsComplete (void)
	Check if SPI transmit shift register is empty.
void	SPI0_SetCallbackHandler (SPI_CALLBACK callback)
	Register an interrupt callback handler.
void	SPI0_EnableInterrupt (SPI_INTERRUPT_SOURCE src)
	Enable a specific SPI interrupt source.
void	SPI0_DisableInterrupt (SPI_INTERRUPT_SOURCE src)
	Disable a specific SPI interrupt source.
bool	SPI0_InterruptFlagIsSet (SPI_INTERRUPT_FLAG flag)
	Check if a specific interrupt flag is set.
void	SPI0_ResetSoftware (void)
	Perform a software reset of the SPI module.
SPI_HWREG_STATUS	SPI0_SetBusSpeed (uint32_t bus_speed, uint32_t clk_frequency)
	Set the SPI bus speed.
uint32_t	SPI0_GetBusSpeed (uint32_t clk_frequency)
	Get the current SPI bus speed.
void	SPI0_SetClockPolarity (bool cpol_high)
	Set the SPI clock polarity.
void	SPI0_SetClockPhase (bool cpha_trailing)
	Set the SPI clock phase.
void	SPI0_SetOperatingMode (SPI_OPERATING_MODE mode)
	Set the SPI operating mode (Host or Client).
void	SPI0_SetBitsPerTransfer (SPI_TRANSFER_SIZE size)
	Set the SPI character/transfer size.
void	SPI0_SetPeripheralSelectMode (SPI_PERIPHERAL_SELECT_MODE mode)
	Set the peripheral select mode.
void	SPI0_ChipSelectSetup (uint8_t chipSelect)
	Setup the chip select line.
void	SPI0_SetPCSDecode (SPI_PCS_DECODE decode)
	Set the PCS decode mode.
void	SPI0_SetModeFault (SPI_MODE_FAULT fault)
	Set the mode fault behavior.
void	SPI0_SetTransferFlowMode (SPI_TRANSFERFLOW_MODE mode)
	Set the transfer flow control mode.
void	SPI0_SetLoopback (SPI_LOOPBACK loopback)
	Set the SPI loopback mode.
void	SPI0_SetDelayBetweenCS (uint8_t delay)
	Set the delay between chip select transitions.
void	SPI0_SetDelayBetweenTransfers (uint8_t delay)
	Set the delay between consecutive SPI transfers.
void	SPI0_SetDelayBeforeSPCK (uint8_t delay)
	Set the delay before SPI clock signal.
void	SPI0_SetCSActiveAfterTransfer (bool cs_active)
	Set chip select to remain active after transfer.
void	SPI0_SetCSNotActiveAfterTransfer (bool cs_not_active)
	Set chip select to not be active after transfer.
void	SPI0_EndTransfer (void)
	Signal the end of the current SPI transfer in Host mode.
void	SPI0_EnableWriteProtection (void)
	Enable write protection for SPI registers.
void	SPI0_DisableWriteProtection (void)
	Disable write protection for SPI registers.
bool	SPI0_WriteProtectionIsEnabled (void)
	Check if write protection is enabled.
bool	SPI0_WriteProtectedIsViolated (void)
	Check if a write protection violation has occurred.
uint8_t	SPI0_GetViolationSourceRegOffset (void)
	Get the register offset of the write protection violation source.

Description

Driver API for SPI (plib_spi0.h)

Macro Definition Documentation

SPI_BAUD_MAX

#define SPI_BAUD_MAX   (0xFFU)

Maximum value for the SPI baud rate register (SCBR field).

Typedef Documentation

SPI_CALLBACK

SPI_CALLBACK

Callback function type for SPI interrupts.

Parameters

intr	The interrupt source that triggered the callback.

Enumeration Type Documentation

SPI_HWREG_STATUS

enum SPI_HWREG_STATUS

Status codes for SPI hardware register operations.

Enumerator
SPI_HWREG_OK	Operation successful
SPI_HWREG_ERROR	Generic error
SPI_HWREG_INVALID_PARAM	Invalid parameter passed
SPI_HWREG_TIMEOUT	Operation timed out
SPI_HWREG_BUSY	Hardware is busy
SPI_HWREG_UNSUPPORTED	Operation not supported

SPI_INTERRUPT_FLAG

enum SPI_INTERRUPT_FLAG

SPI interrupt flags.

Enumerator
SPI_FLAG_RDRF
SPI_FLAG_TDRE
SPI_FLAG_MODF
SPI_FLAG_OVRES
SPI_FLAG_NSSR
SPI_FLAG_TXEMPTY
SPI_FLAG_UNDES
SPI_FLAG_ALL

SPI_INTERRUPT_SOURCE

enum SPI_INTERRUPT_SOURCE

SPI interrupt sources.

Enumerator
SPI_INTERRUPT_NONE
SPI_INTERRUPT_RDRF
SPI_INTERRUPT_TDRE
SPI_INTERRUPT_MODF
SPI_INTERRUPT_OVRES
SPI_INTERRUPT_NSSR
SPI_INTERRUPT_TXEMPTY
SPI_INTERRUPT_UNDES
SPI_INTERRUPT_ALL

SPI_LOOPBACK

enum SPI_LOOPBACK

Internal loopback mode: disabled for normal operation, enabled for self-test.

Enumerator
SPI_LOOPBACK_DISABLE	Normal SPI operation
SPI_LOOPBACK_ENABLE	Internal MOSI-to-MISO loopback (Host mode)

SPI_MODE_FAULT

enum SPI_MODE_FAULT

Mode fault detection: enable to detect host conflicts.

Enumerator
SPI_MODE_FAULT_ENABLE	Detect mode faults (Host mode only)
SPI_MODE_FAULT_DISABLE	Disable mode fault detection

SPI_OPERATING_MODE

enum SPI_OPERATING_MODE

SPI operating modes.

Enumerator
SPI_CLIENT_MODE
SPI_HOST_MODE

SPI_PCS_DECODE

enum SPI_PCS_DECODE

Chip select decoding mode: direct NPCS pins or external decoder.

Enumerator
SPI_CHIP_SELECT_DIRECT	Direct NPCS pins (0-3)
SPI_CHIP_SELECT_DECODE	External decoder (0-14 peripherals)

SPI_PERIPHERAL_SELECT_MODE

enum SPI_PERIPHERAL_SELECT_MODE

Peripheral select mode: fixed or variable per transfer.

Enumerator
SPI_FIXED_PERIPHERAL_SELECT	Single peripheral defined in SPI_MR.PCS
SPI_VARIABLE_PERIPHERAL_SELECT	PCS encoded in SPI_TDR for each transfer

SPI_TRANSFER_SIZE

enum SPI_TRANSFER_SIZE

SPI character/transfer size options.

Enumerator
SPI_TRANSFER_SIZE_8BIT
SPI_TRANSFER_SIZE_9BIT
SPI_TRANSFER_SIZE_10BIT
SPI_TRANSFER_SIZE_11BIT
SPI_TRANSFER_SIZE_12BIT
SPI_TRANSFER_SIZE_13BIT
SPI_TRANSFER_SIZE_14BIT
SPI_TRANSFER_SIZE_15BIT
SPI_TRANSFER_SIZE_16BIT

SPI_TRANSFERFLOW_MODE

enum SPI_TRANSFERFLOW_MODE

Transfer flow control: continuous or wait-for-read.

Enumerator
SPI_TRANSFER_FLOW_NORMAL	Continuous flow (no read requirement)
SPI_TRANSFER_FLOW_WAIT_FOR_READ	Stall until receive data is read

Function Documentation

SPI0_ChipSelectSetup()

void SPI0_ChipSelectSetup

(

uint8_t

chipSelect

)

Setup the chip select line.

Configures the PCS (Peripheral Chip Select) field in SPI_MR to select which chip select line(s) will be used for Fixed Peripheral Select mode. In Variable mode, the PCS is encoded per-transfer in SPI_TDR.

The SPI0 peripheral supports 4 chip select outputs (NPCS0-3), or up to 15 peripherals when using external chip select decoding.

Parameters

chipSelect

The chip select value to configure: 0: NPCS0 selected 1: NPCS1 selected 2: NPCS2 selected 3: NPCS3 selected With external decoding, values 0-14 can select up to 15 peripherals

Note

This function sets SPI_MR.PCS field and applies to Fixed Peripheral Select mode.

In Variable mode, PCS must be encoded in SPI_TDR for each transfer.

The actual PCS output state depends on CSAAT (Chip Select Active After Transfer) and CSNAAT (Chip Select Not Active After Transfer) bits in SPI_CSRx.

External chip select decoding must be enabled via SetPCSDecode() to use 15 peripherals.

In Client mode, chip select is not used (NSS is an input).

See also

SPI0_SetPCSDecode() to enable external chip select decoding.

SPI0_SetPeripheralSelectMode() for Fixed vs. Variable mode.

SPI0_Disable()

void SPI0_Disable

(

void

)

Disable the SPI module.

Disables the SPI0 peripheral by setting the SPIDIS bit in SPI_CR. The function ensures that ongoing transfers are completed before shutdown. After disabling, the peripheral clock can be switched off. Register configuration is preserved.

Note

Wait for TXEMPTY flag before disabling to ensure all transfers complete.

Unlike SPI0_ResetSoftware, this does not reset configuration registers.

Returns

void

SPI0_DisableInterrupt()

void SPI0_DisableInterrupt

(

SPI_INTERRUPT_SOURCE

src

)

Disable a specific SPI interrupt source.

Disables the specified interrupt(s) by setting the corresponding bits in SPI_IDR (Interrupt Disable Register). When disabled, SPI interrupts of those types will not trigger the ISR or invoke the callback, but the interrupt flag(s) may still be set in SPI_SR and can be polled.

Parameters

src	One or more interrupt source(s) (OR'd together) to disable. Example: DisableInterrupt(SPI_INTERRUPT_RDRF | SPI_INTERRUPT_TDRE)

Note

Disabling an interrupt does not clear its flag in SPI_SR; flags must be read via InterruptFlagIsSet() if status polling is used.

Multiple interrupt sources can be disabled simultaneously.

Use this function when switching from interrupt-driven to polling-based operation, or to selectively disable specific interrupts.

Disabling does not affect the SPI module functionality, only interrupt signaling.

See also

SPI0_EnableInterrupt() to enable specific sources.

SPI0_InterruptFlagIsSet() to poll interrupt status.

SPI_INTERRUPT_SOURCE for available sources.

SPI0_DisableWriteProtection()

void SPI0_DisableWriteProtection

(

void

)

Disable write protection for SPI registers.

Disables write protection by clearing the WPEN (Write Protection Enable) bit in SPI_WPMR. When disabled, protected registers can be freely modified.

Use this function when:

• Reconfiguring SPI settings during initialization
• Changing operating modes (Host to Client)
• Adjusting clock speed or transfer parameters
• Re-enabling write protection after configuration

Note

After disabling, configure all required SPI registers, then call EnableWriteProtection() to re-enable protection.

Only disable write protection when necessary; keep it enabled in production to prevent accidental corruption of critical settings.

The disable command is typically issued during system initialization.

Write protection applies to both firmware and hardware; disabling affects both.

See also

SPI0_EnableWriteProtection() to re-enable protection.

SPI0_WriteProtectionIsEnabled() to check current state.

SPI0_Enable()

void SPI0_Enable

(

void

)

Enable the SPI module.

Enables the SPI0 peripheral by setting the SPIEN bit in SPI_CR. After enabling, the TDRE and TXEMPTY flags are automatically set, allowing data transfers to begin. The peripheral clock must be enabled via PMC before calling this function.

Note

TDRE and TXEMPTY flags are automatically set when SPI is enabled.

This function does not configure the SPI mode or data format; use the configuration functions (SetOperatingMode, SetBitsPerTransfer, etc.) before enabling.

Returns

void

SPI0_EnableInterrupt()

void SPI0_EnableInterrupt

(

SPI_INTERRUPT_SOURCE

src

)

Enable a specific SPI interrupt source.

Enables the specified interrupt(s) by setting the corresponding bits in SPI_IER (Interrupt Enable Register). When enabled, SPI interrupts will trigger the ISR, which invokes the registered callback (if set via SetCallbackHandler).

Available interrupt sources (SPI_INTERRUPT_SOURCE):

• SPI_INTERRUPT_RDRF: Receive Data Register Full
• SPI_INTERRUPT_TDRE: Transmit Data Register Empty
• SPI_INTERRUPT_MODF: Mode Fault Error (Host mode only)
• SPI_INTERRUPT_OVRES: Overrun Error (occurs when RDR not read before new data)
• SPI_INTERRUPT_NSSR: NSS Rising (Host mode only; NSS high detection)
• SPI_INTERRUPT_TXEMPTY: Transmit Registers Empty (Host mode)
• SPI_INTERRUPT_UNDES: Underrun Error (Client mode only)

Parameters

src	One or more interrupt source(s) (OR'd together) to enable. Example: EnableInterrupt(SPI_INTERRUPT_RDRF | SPI_INTERRUPT_TDRE)

Note

Before enabling interrupts, ensure the interrupt controller is configured to route SPI0 interrupts to the CPU.

The SPI0_SetCallbackHandler() must be called before enabling interrupts to register the callback function.

Multiple interrupt sources can be enabled simultaneously.

Some interrupts are mode-specific (e.g., MODF only in Host mode).

See also

SPI0_DisableInterrupt() to disable specific sources.

SPI0_SetCallbackHandler() to register the callback.

SPI_INTERRUPT_SOURCE for available sources.

SPI0_EnableWriteProtection()

void SPI0_EnableWriteProtection

(

void

)

Enable write protection for SPI registers.

Enables write protection by setting the WPEN (Write Protection Enable) bit in SPI_WPMR (Write Protection Mode Register). When enabled, protected registers cannot be modified; attempts to write will trigger a write protection violation.

Protected registers include:

• SPI_MR (Mode Register)
• SPI_CR (Control Register with SPIDIS)
• SPI_CSR0-3 (Chip Select Registers)

Write protection helps prevent accidental or malicious modification of critical SPI configuration in safety-critical or automotive applications.

Note

To write to protected registers, first disable write protection via DisableWriteProtection().

Write protection can be re-enabled after configuration is complete.

WriteProtectionIsEnabled() can be used to verify current protection state.

WriteProtectedIsViolated() detects if a write to protected register occurred.

Write protection state is preserved across SPI reset (not cleared by ResetSoftware).

See also

SPI0_DisableWriteProtection() to disable protection for reconfiguration.

SPI0_WriteProtectionIsEnabled() to check current state.

SPI0_WriteProtectedIsViolated() to detect violation attempts.

SPI0_EndTransfer()

void SPI0_EndTransfer

(

void

)

Signal the end of the current SPI transfer in Host mode.

Sets the LASTXFER (Last Transfer) bit in SPI_CR to signal that the current transfer is the final one in a sequence. This is used in Host mode to indicate when to deassert the chip select (NPCS) signal after the current transmission completes.

Use case: When communicating with a Client device that requires NPCS to be deasserted between transactions, this function signals the end of the current transaction so that the next NPCS assertion starts a new transaction.

In Host mode with fixed chip select:

• If LASTXFER is set before transmission, NPCS is deasserted after the last bit is sent
• If LASTXFER is not set, NPCS remains asserted for the next transfer (continuous transmission)

Note

This function applies to Host mode (MSTR=1) operation only.

Call this function before or during the final transmission in a sequence.

The bit is typically set via SPI_Send() when transmitting the last data word, or called explicitly before the final send operation.

LASTXFER only affects chip select behavior; it does not stop or abort the transfer.

In Client mode, this field is not used.

See also

SPI0_Send() for data transmission operations.

SPI0_SetOperatingMode() to configure Host/Client mode.

SPI0_GetBusSpeed()

uint32_t SPI0_GetBusSpeed

(

uint32_t

clk_frequency

)

Get the current SPI bus speed.

Reads the SCBR (Serial Clock Bit Rate) value from SPI_CSR0 and calculates the actual SPI serial clock (SPCK) frequency. The calculation is: SPCK = peripheral_clock / SCBR

Parameters

clk_frequency

The peripheral clock frequency in Hz.

Returns

The current SPI bus speed (SPCK frequency) in Hz.

Note

If SCBR is 0 (uninitialized), this function will set SCBR to 1 and return clk_frequency.

Call SetBusSpeed() to initialize SCBR before reading the speed.

This function reads from SPI_CSR0 and reflects the configuration for chip select 0.

See also

SPI0_SetBusSpeed() to configure the speed.

SPI0_GetViolationSourceRegOffset()

uint8_t SPI0_GetViolationSourceRegOffset

(

void

)

Get the register offset of the write protection violation source.

Reads the WPVSRC (Write Protection Violation Source) field in SPI_WPSR to determine which protected register was the target of the failed write attempt. This helps identify which configuration register code was trying to modify when protection was enabled.

Typical protected register offsets:

• 0x00: SPI_MR (Mode Register)
• 0x04: SPI_CR (Control Register)
• 0x34-0x40: SPI_CSR0-3 (Chip Select Registers)

Returns

The byte offset of the protected register that was targeted by the failed write attempt (within the SPI peripheral register map).

Note

Only meaningful when WriteProtectedIsViolated() returns true.

Use this to log or handle the specific register that was targeted.

The offset is relative to the SPI0 base address.

In debugging, this helps identify which part of the configuration code attempted to modify protected registers.

Multiple violations may be recorded; read this after each detected violation.

See also

SPI0_WriteProtectedIsViolated() to detect if a violation occurred.

SPI0_DisableWriteProtection() to temporarily disable protection.

SPI0_InterruptFlagIsSet()

bool SPI0_InterruptFlagIsSet

(

SPI_INTERRUPT_FLAG

flag

)

Check if a specific interrupt flag is set.

Tests the specified interrupt flag in SPI_SR (Status Register) to determine if the corresponding event has occurred. This is useful for polling-based operation or to manually check status within an ISR.

Available interrupt flags (SPI_INTERRUPT_FLAG):

• SPI_FLAG_RDRF: Receive Data Register Full (data available in SPI_RDR)
• SPI_FLAG_TDRE: Transmit Data Register Empty (SPI_TDR can accept new data)
• SPI_FLAG_MODF: Mode Fault Error detected (Host mode)
• SPI_FLAG_OVRES: Overrun Error (RDR not read before new data arrived)
• SPI_FLAG_NSSR: NSS Rising edge detected (Host mode)
• SPI_FLAG_TXEMPTY: Transmit shift register empty (no data being transmitted)
• SPI_FLAG_UNDES: Underrun Error (Client mode; no data ready to shift out)

Parameters

flag	The interrupt flag to check (SPI_INTERRUPT_FLAG value).

Returns

true if the specified flag is set in SPI_SR; false otherwise.

Note

Interrupt flags are set by hardware; some are cleared by reading registers (e.g., RDRF cleared by reading SPI_RDR), others require explicit handling.

Use this function in polling mode to avoid using interrupts.

Multiple flags can be set simultaneously; check them individually.

OVRES and other error flags should be cleared (usually via SPI_SR read) before resuming normal operation.

See also

SPI_INTERRUPT_FLAG for available flag values.

SPI0_Receive()

uint16_t SPI0_Receive

(

void

)

Receive a single data word via SPI.

Reads data from the SPI_RDR (Receive Data Register) that was shifted in from the SPI bus (MISO line for Host mode, MOSI line for Client mode). The data was collected during the previous transfer. The actual number of bits received (8-16) is determined by the bits per transfer configuration (SPI_CSRx.BITS).

Reading SPI_RDR clears the RDRF (Receive Data Register Full) flag. If new data arrives before the previous data is read, the OVRES (Overrun Error) flag is set in SPI_SR.

Returns

The received data word (8 to 16 bits; upper bits are zero-padded for smaller transfers).

Note

Check SPI0_RxIsReady() before calling to ensure RDR contains valid data.

This function is non-blocking; it reads the current RDR value without waiting.

In Host mode, data cannot be received without transmitting (full-duplex operation).

If OVRES flag is set, read SPI_SR to clear it before continuing transfers.

Receiving requires a prior SPI0_Send() call to initiate the transfer.

SPI0_ResetSoftware()

void SPI0_ResetSoftware

(

void

)

Perform a software reset of the SPI module.

Resets the SPI module to its initial state by setting the SWRST bit in SPI_CR. After reset, all registers return to their default values:

• SPI is disabled (SPIEN = 0)
• Operating mode is set to Client mode (MSTR = 0)
• All chip select registers (SPI_CSR0-3) are reset
• All interrupt flags are cleared
• All pending transfers are aborted

After calling this function, the SPI peripheral must be reconfigured before use.

Note

This is a non-destructive reset; SPI configuration registers are reset, not preserved.

Use SPI0_Disable() if you need to stop transfers without losing configuration.

After reset, always reconfigure:

1. Operating mode (SetOperatingMode)
2. Bus speed for Host mode (SetBusSpeed)
3. Clock polarity and phase (SetClockPolarity, SetClockPhase)
4. Data size (SetBitsPerTransfer) Then call SPI0_Enable() to restart operation.

Returns

void

SPI0_RxIsReady()

bool SPI0_RxIsReady

(

void

)

Check if SPI receiver is ready.

Tests the RDRF (Receive Data Register Full) flag in SPI_SR to determine if the receiver has data available to read. RDRF is set when data is transferred from the internal shift register to SPI_RDR after a complete transfer.

Returns

true if RDRF flag is set and data is available in SPI_RDR; false otherwise.

Note

Use this function in polling mode before calling SPI0_Receive().

In interrupt mode, SPI_INTERRUPT_RDRF can be enabled to signal data availability.

RDRF is cleared when SPI_RDR is read via SPI0_Receive().

If RDRF is set but data is not read before the next transfer completes, the OVRES (Overrun Error) flag will be set.

SPI0_Send()

void SPI0_Send

(

uint16_t

data

)

Send a single data word via SPI.

Writes data to the SPI_TDR (Transmit Data Register) to initiate a data transfer. The data is immediately transferred to the internal shift register, and transmission begins on the SPI bus (MOSI line for Host mode, MISO line for Client mode). The actual number of bits transmitted (8-16) is determined by the bits per transfer configuration (SPI_CSRx.BITS).

In Host mode, the SPCK is driven by the baud rate generator. In Client mode, transmission is synchronized by the external SPCK from the Host.

Parameters

data	The data word to transmit (8 to 16 bits; upper bits are ignored for smaller transfers).

Note

Check SPI0_TxIsReady() before calling to ensure TDR is ready for new data.

In Host mode with Fixed Peripheral Select (PS=0), chip select is defined by SPI_MR.PCS.

In Host mode with Variable Peripheral Select (PS=1), chip select must be encoded in data.

TDRE flag is cleared when data is written; it's set again when data is loaded into the shift register.

If no receive data is needed, dummy data (typically 0xFF) can be sent.

Returns

void

SPI0_SetBitsPerTransfer()

void SPI0_SetBitsPerTransfer

(

SPI_TRANSFER_SIZE

size

)

Set the SPI character/transfer size.

Configures the BITS field in SPI_CSR0 to set the number of bits transferred per SPI transaction. Supported sizes are 8 to 16 bits, corresponding to the SPI_TRANSFER_SIZE enum values (0-8).

The actual data width in SPI_TDR and SPI_RDR is still 16 bits, but only the configured number of bits are actually transmitted/received on the SPI bus. Extra bits are padded with zeros or ignored.

Parameters

size	Number of bits per transfer (SPI_TRANSFER_SIZE enum): SPI_TRANSFER_SIZE_8BIT: 8 bits SPI_TRANSFER_SIZE_9BIT: 9 bits ... up to SPI_TRANSFER_SIZE_16BIT: 16 bits

Note

This setting affects both transmit and receive operations.

Each chip select can have its own BITS setting in SPI_CSRx.

Host and Client must use the same BITS setting to communicate correctly.

BITS must be configured before transmitting data for correct transfer size.

The BITS field is in SPI_CSR0 and applies to chip select 0.

See also

SPI_TRANSFER_SIZE for supported bit sizes.

SPI0_SetBusSpeed()

SPI_HWREG_STATUS SPI0_SetBusSpeed	(	uint32_t	bus_speed,
		uint32_t	clk_frequency )

Set the SPI bus speed.

Configures the SPI clock bit rate (baud rate) by calculating and setting the SCBR (Serial Clock Bit Rate) field in SPI_CSR0. The SCBR divides the peripheral clock to generate the SPI serial clock (SPCK). The baud rate is calculated as: SPCK = peripheral_clock / SCBR

The SCBR value is computed as: SCBR = peripheral_clock / bus_speed and is clamped to the range [1, 255] (SPI_BAUD_MAX).

Parameters

bus_speed	The desired SPI bus speed in Hz (SPCK frequency).
clk_frequency	The peripheral clock frequency in Hz.

Returns

Status code (SPI_HWREG_STATUS):

• SPI_HWREG_OK: Configuration successful
• SPI_HWREG_INVALID_PARAM: bus_speed is 0, clk_frequency is 0, or bus_speed > clk_frequency

Note

This function applies only to Host mode (MSTR=1); Client mode uses external SPCK.

The actual SPCK frequency may differ due to divisor rounding.

Use GetBusSpeed() to verify the actual configured speed.

SCBR value of 0 at reset will cause unpredictable results; always set before first transfer.

This function updates SPI_CSR0 and affects all transfers using chip select 0.

See also

SPI0_GetBusSpeed() to read the actual configured speed.

SPI0_SetCallbackHandler()

void SPI0_SetCallbackHandler

(

SPI_CALLBACK

callback

)

Register an interrupt callback handler.

Registers a user-defined callback function to be invoked from the SPI interrupt service routine (ISR) when any enabled SPI interrupt occurs. The callback receives the interrupt source (SPI_INTERRUPT_SOURCE) as a parameter.

Multiple interrupts can be enabled simultaneously (RDRF, TDRE, MODF, OVRES, etc.), and the same callback will be called for all enabled sources. The application must check the interrupt source parameter to determine which event occurred.

Parameters

callback

Function pointer to the callback handler: typedef void (*SPI_CALLBACK)(uint8_t intr); where intr contains the interrupt source flags (SPI_INTERRUPT_SOURCE).

Note

Interrupt callbacks are invoked from ISR context (high priority). Keep callback code short and fast to avoid latency.

The callback must be registered before enabling interrupts with EnableInterrupt().

Pass NULL to disable callback invocation (though interrupts remain enabled).

Each SPI instance has its own callback handler; SPI0_SetCallbackHandler() sets the handler for SPI0 only.

See also

SPI0_EnableInterrupt() to enable specific interrupt sources.

SPI_CALLBACK for callback function signature.

SPI0_SetClockPhase()

void SPI0_SetClockPhase

(

bool

cpha_trailing

)

Set the SPI clock phase.

Configures the NCPHA (inverted Clock Phase) bit in SPI_CSR0 to set which clock edge is used for data capture and shifting:

CPHA = 0 (Leading edge capture, NCPHA=1):

• Data is sampled on the leading edge of SPCK
• Data is shifted out on the trailing edge of SPCK

CPHA = 1 (Trailing edge capture, NCPHA=0):

• Data is sampled on the trailing edge of SPCK
• Data is shifted out on the leading edge of SPCK

The combination of CPOL and CPHA selects the SPI mode (0-3):

• Mode 0: CPOL=0, CPHA=0 | Mode 1: CPOL=0, CPHA=1
• Mode 2: CPOL=1, CPHA=0 | Mode 3: CPOL=1, CPHA=1

Parameters

cpha_trailing

true for CPHA=1 (trailing edge capture, NCPHA cleared); false for CPHA=0 (leading edge capture, NCPHA set).

Note

Host and Client devices must use the same CPHA setting to communicate correctly.

Use SetClockPolarity() to configure CPOL and complete the SPI mode selection.

This updates SPI_CSR0 and affects transfers on chip select 0.

The hardware register uses NCPHA (inverted CPHA); when cpha_trailing=true, NCPHA is cleared.

See also

SPI0_SetClockPolarity() to configure clock polarity (CPOL).

SPI0_SetClockPolarity()

void SPI0_SetClockPolarity

(

bool

cpol_high

)

Set the SPI clock polarity.

Configures the CPOL (Clock Polarity) bit in SPI_CSR0 to set the idle state of the SPCK signal:

CPOL = 0 (Clock idles LOW):

• SPCK is normally low when idle
• Data is sampled/shifted on the rising edge of SPCK
• Combined with CPHA determines the complete SPI mode (0, 1, 2, or 3)

CPOL = 1 (Clock idles HIGH):

• SPCK is normally high when idle
• Data is sampled/shifted on the falling edge of SPCK
• Combined with CPHA determines the complete SPI mode (0, 1, 2, or 3)

Parameters

cpol_high

true for CPOL=1 (clock idles HIGH); false for CPOL=0 (clock idles LOW).

Note

Host and Client devices must use the same CPOL setting to communicate correctly.

Use SetClockPhase() to configure CPHA and complete the SPI mode selection.

This updates SPI_CSR0 and affects transfers on chip select 0.

See also

SPI0_SetClockPhase() to configure clock phase (CPHA).

SPI0_SetCSActiveAfterTransfer()

void SPI0_SetCSActiveAfterTransfer

(

bool

cs_active

)

Set chip select to remain active after transfer.

Configures the CSAAT (Chip Select Active After Transfer) bit in SPI_CSR0 to control whether the chip select (NPCS) remains active (low) after the current transfer completes. This is useful for multi-byte transfers where chip select should stay asserted between consecutive bytes.

CSAAT = 0 (Default - Deasserted after transfer):

• NPCS goes high after the current transfer completes
• Used for single transfers or when chip select must deassert between operations

CSAAT = 1 (Active after transfer):

• NPCS remains low after the current transfer completes
• Used for consecutive transfers without deasserttion
• Chip select stays asserted until explicitly deasserted or next transfer uses different PCS

Parameters

cs_active

true to keep NPCS active (low) after transfer; false to deassert NPCS (go high) after transfer.

Note

This function updates SPI_CSR0 and applies to the current chip select.

Applies to Host mode only.

Use with SPI0_EndTransfer() to explicitly control when chip select is deasserted.

Each chip select can have its own CSAAT setting in SPI_CSRx.

See also

SPI0_SetCSNotActiveAfterTransfer() to set the complementary behavior.

SPI0_EndTransfer() to explicitly deassert chip select.

SPI0_SetCSNotActiveAfterTransfer()

void SPI0_SetCSNotActiveAfterTransfer

(

bool

cs_not_active

)

Set chip select to not be active after transfer.

Configures the CSNAAT (Chip Select Not Active After Transfer) bit in SPI_CSR0 to control whether the chip select (NPCS) should be deasserted (driven high) after the current transfer completes. This provides an alternative way to manage chip select behavior compared to CSAAT.

CSNAAT = 0 (CS active after transfer):

• NPCS remains low after the current transfer completes
• Equivalent to CSAAT = 1
• Set when cs_not_active = false

CSNAAT = 1 (CS not active after transfer):

• NPCS goes high after the current transfer completes
• Equivalent to CSAAT = 0
• Set when cs_not_active = true

Parameters

cs_not_active

true to set CSNAAT bit (NPCS deasserted after transfer); false to clear CSNAAT bit (NPCS remains active after transfer).

Note

This function updates SPI_CSR0 and applies to the current chip select.

Applies to Host mode only.

CSNAAT is the logical inverse of CSAAT; they are complementary bits.

Each chip select can have its own CSNAAT setting in SPI_CSRx.

See also

SPI0_SetCSActiveAfterTransfer() to set the complementary behavior (uses CSAAT).

SPI0_EndTransfer() to explicitly deassert chip select.

SPI0_SetDelayBeforeSPCK()

void SPI0_SetDelayBeforeSPCK

(

uint8_t

delay

)

Set the delay before SPI clock signal.

Configures the DLYBS (Delay Before SPCK) field in SPI_CSR0 to set the minimum delay between chip select assertion (NPCS low) and the first rising edge of the SPI clock (SPCK). This allows Client devices time to prepare after being selected.

The delay is specified in peripheral clock cycles: delay = DLYBS * peripheral_clock_period

Typical use cases:

• Meeting minimum tSU (setup) timing requirements
• Allowing Client device setup time after chip select assertion
• Ensuring reliable data capture on the first clock edge

Parameters

delay

The delay in peripheral clock cycles (0-255): 0: Minimum delay (no additional cycles) 1: 1 peripheral clock cycle ... 255: 255 peripheral clock cycles

Note

This function updates SPI_CSR0 and applies to the current chip select.

Applies to Host mode only.

Each chip select can have its own DLYBS value in SPI_CSRx.

See also

SPI0_SetDelayBetweenTransfers() to set delay between consecutive transfers.

SPI0_SetDelayBetweenCS()

void SPI0_SetDelayBetweenCS

(

uint8_t

delay

)

Set the delay between chip select transitions.

Configures the DLYBCS (Delay Between Chip Selects) field in SPI_MR to set the minimum delay between the deassertion of one chip select (NPCS) and the assertion of another NPCS. This delay allows Client devices time to deactivate before the next device is selected.

The delay is specified in peripheral clock cycles: delay = (DLYBCS + 1) * peripheral_clock_period

Typical use cases:

• Allowing Client device settling time between transfers
• Meeting minimum tCS (chip select setup) timing requirements
• Preventing bus contention when switching between multiple Clients
• Matching external Client device deactivation delays

Parameters

delay

The delay in peripheral clock cycles (0-255): 0: Minimum delay (1 cycle) 1: 2 peripheral clock cycles ... 255: 256 peripheral clock cycles

Note

This field is common to all chip selects (NPCS0-3); only one value.

DLYBCS is applied globally between any two chip select changes.

If only one Client is used, DLYBCS does not need to be configured.

Typical values range from 5-20 cycles for most serial devices.

This function updates SPI_MR and applies to Host mode only.

See also

SPI0_ChipSelectSetup() to select which chip select to use.

SPI0_SetDelayBetweenTransfers()

void SPI0_SetDelayBetweenTransfers

(

uint8_t

delay

)

Set the delay between consecutive SPI transfers.

Configures the DLYBCT (Delay Between Consecutive Transfers) field in SPI_CSR0 to set the minimum delay between the end of one transfer and the start of the next. This delay applies only when the same chip select is used for consecutive transfers.

The delay is specified in peripheral clock cycles: delay = (DLYBCT + 1) * peripheral_clock_period

Typical use cases:

• Allowing Client device processing time between transfers
• Meeting minimum tDH (data hold) timing requirements
• Ensuring Client readiness for the next transfer

Parameters

delay

The delay in peripheral clock cycles (0-255): 0: Minimum delay (1 cycle) 1: 2 peripheral clock cycles ... 255: 256 peripheral clock cycles

Note

This function updates SPI_CSR0 and applies to the current chip select.

Applies to Host mode only.

Each chip select can have its own DLYBCT value in SPI_CSRx.

See also

SPI0_SetDelayBetweenCS() to set delay between different chip selects.

SPI0_SetLoopback()

void SPI0_SetLoopback

(

SPI_LOOPBACK

loopback

)

Set the SPI loopback mode.

Configures the LLB (Local Loopback) bit in SPI_MR to enable or disable internal loopback mode. Loopback is useful for self-testing and debugging without requiring external hardware connections.

Loopback Disabled (SPI_LOOPBACK_DISABLE):

• LLB = 0 in SPI_MR
• Normal SPI operation
• MOSI line output is not connected to MISO line input
• Data received depends on external SPI devices

Loopback Enabled (SPI_LOOPBACK_ENABLE):

• LLB = 1 in SPI_MR
• Internal loopback: MOSI output is fed directly to MISO input
• Data sent is immediately received (full-duplex loopback)
• Useful for self-test and verifying SPI timing/configuration
• External chip selects and slave devices are still active (but ignored for loopback)

Parameters

loopback

SPI_LOOPBACK_DISABLE for normal operation; SPI_LOOPBACK_ENABLE for internal loopback testing.

Note

Loopback applies only to Host mode (MSTR=1).

In loopback mode, MISO still reflects MOSI data regardless of external devices.

Clock polarity (CPOL) and phase (NCPHA) still apply in loopback mode.

Useful for verifying driver functionality before connecting to actual hardware.

See also

SPI0_Send() and SPI0_Receive() for data transfer operations.

SPI0_SetModeFault()

void SPI0_SetModeFault

(

SPI_MODE_FAULT

fault

)

Set the mode fault behavior.

Configures the MODFDIS (Mode Fault Detection Disable) bit in SPI_MR to enable or disable mode fault detection. Mode fault detection helps identify configuration conflicts in Host mode.

Mode Fault Enabled (SPI_MODE_FAULT_ENABLE):

• MODFDIS = 0 in SPI_MR
• If an external Host tries to write to the SPI bus while SPI0 is operating in Host mode, a collision is detected
• SPI0 automatically disables its output (MOSI, SPCK) and asserts the MODF (Mode Fault) flag in SPI_SR
• Useful for multi-Host systems to detect arbitration conflicts

Mode Fault Disabled (SPI_MODE_FAULT_DISABLE):

• MODFDIS = 1 in SPI_MR
• Mode fault detection is bypassed
• Useful for single-Host systems where no conflicts are possible
• Reduces interrupt overhead if MODF interrupt is not needed

Parameters

fault

SPI_MODE_FAULT_ENABLE to detect mode faults; SPI_MODE_FAULT_DISABLE to bypass detection.

Note

Mode fault detection applies only to Host mode (MSTR=1).

When MODF is asserted, the SPI must be disabled and reconfigured.

For single-master systems, mode fault detection can be safely disabled.

MODF flag can be monitored via interrupt (SPI_INTERRUPT_MODF) or polling.

See also

SPI0_SetOperatingMode() to configure Host/Client mode.

SPI0_EnableInterrupt() to enable MODF interrupt (SPI_INTERRUPT_MODF).

SPI0_SetOperatingMode()

void SPI0_SetOperatingMode

(

SPI_OPERATING_MODE

mode

)

Set the SPI operating mode (Host or Client).

Configures the MSTR (Master) bit in SPI_MR to set the SPI operating mode:

Host Mode (SPI_HOST_MODE):

• MSTR = 1 in SPI_MR
• SPCK pin is driven by internal baud rate generator
• NPCS0-3 pins are driven as outputs (chip select signals)
• MOSI line is driven by transmitter; MISO is receiver input
• Full control of data transfers and timing

Client Mode (SPI_CLIENT_MODE):

• MSTR = 0 in SPI_MR
• SPCK pin is input, receives clock from Host
• NPCS0 pin becomes input (NSS - Slave Select signal)
• NPCS1-3 pins are not driven (can be used for other purposes)
• MISO line is driven by transmitter; MOSI is receiver input
• Data transfers are controlled by Host via NSS and SPCK

Parameters

mode	SPI_HOST_MODE for Host (master) operation; SPI_CLIENT_MODE for Client (slave) operation.

Note

The operating mode must be set before enabling the SPI (SPI0_Enable).

Host mode requires the peripheral clock to be enabled; Client mode can operate asynchronously with the core clock.

In Host mode, baud rate must be configured (SetBusSpeed); not applicable in Client mode.

SPI0_ResetSoftware sets the mode to Client mode after reset.

See also

SPI_OPERATING_MODE for mode values.

SPI0_SetPCSDecode()

void SPI0_SetPCSDecode

(

SPI_PCS_DECODE

decode

)

Set the PCS decode mode.

Configures the PCSDEC (Peripheral Chip Select Decode) bit in SPI_MR to enable or disable external chip select decoding via an external decoder/demultiplexer.

Direct Mode (SPI_CHIP_SELECT_DIRECT):

• PCSDEC = 0 in SPI_MR
• SPI outputs PCS value directly on NPCS0-3 pins
• Supports 4 peripherals (0-3) or multiple discrete chip selects
• Simpler but uses more SPI pins

Decoded Mode (SPI_CHIP_SELECT_DECODE):

• PCSDEC = 1 in SPI_MR
• SPI outputs PCS value to an external 4-to-15 decoder/demultiplexer
• NPCS0-3 pins connect to decoder inputs
• Decoder outputs 15 chip select lines (one line stays high as default)
• Supports up to 15 peripherals (values 0-14) without additional SPI pins
• Requires external decoder hardware

Parameters

decode

SPI_CHIP_SELECT_DIRECT to use NPCS pins directly; SPI_CHIP_SELECT_DECODE to use external decoder.

Note

External chip select decoding requires additional hardware (decoder IC).

Decoding is useful for multi-peripheral applications to save pins.

SPI_CSRx registers are still indexed by hardware NPCS0-3 (not decoded peripherals).

Compatible peripherals must be connected to decoder outputs corresponding to their NPCS group (0-3, 4-7, 8-11, 12-14).

See also

SPI0_ChipSelectSetup() to select the chip select value.

SPI0_SetPeripheralSelectMode()

void SPI0_SetPeripheralSelectMode

(

SPI_PERIPHERAL_SELECT_MODE

mode

)

Set the peripheral select mode.

Configures the PS (Peripheral Select) bit in SPI_MR to select between Fixed and Variable peripheral selection modes. This mode applies to Host mode operation.

Fixed Peripheral Select Mode (SPI_FIXED_PERIPHERAL_SELECT):

• PS = 0 in SPI_MR
• SPI communicates with a single peripheral defined by SPI_MR.PCS
• SPI_TDR.PCS field is ignored during transmission
• Simpler to use for single-peripheral applications
• Requires reconfiguring SPI_MR.PCS to switch peripherals

Variable Peripheral Select Mode (SPI_VARIABLE_PERIPHERAL_SELECT):

• PS = 1 in SPI_MR
• SPI can communicate with multiple peripherals without reconfiguring SPI_MR
• SPI_TDR.PCS field selects the peripheral for each transfer
• More flexible for multi-peripheral scenarios
• Requires encoding PCS value in SPI_TDR upper bits during transmission

Parameters

mode	SPI_FIXED_PERIPHERAL_SELECT for single peripheral; SPI_VARIABLE_PERIPHERAL_SELECT for multiple peripherals.

Note

This function is only meaningful in Host mode (MSTR=1).

In Client mode, this field is not used.

For Variable mode with DMA, use 32-bit SPI_TDR writes to encode PCS.

See also

SPI0_SetOperatingMode() to configure Host/Client mode.

SPI0_ChipSelectSetup() to manage chip select lines.

SPI0_SetTransferFlowMode()

void SPI0_SetTransferFlowMode

(

SPI_TRANSFERFLOW_MODE

mode

)

Set the transfer flow control mode.

Configures the WDRBT (Wait Data Read Before Transfer) bit in SPI_MR to control whether new data can be written to SPI_TDR before the previous receive data is read.

Normal Flow (SPI_TRANSFER_FLOW_NORMAL):

• WDRBT = 0 in SPI_MR
• New data can be written to SPI_TDR at any time
• A new transfer starts immediately after the current one completes
• If receive data is not read before a new transfer completes, OVRES (Overrun) error occurs
• Useful for transmit-only applications or when polling for received data

Wait-for-Read Flow (SPI_TRANSFER_FLOW_WAIT_FOR_READ):

• WDRBT = 1 in SPI_MR
• New data can only be written to SPI_TDR after the previous receive data is read
• This prevents data loss by stalling the transfer pipeline
• Useful for applications that must process each receive byte before receiving the next
• Reduces OVRES error risk in interrupt-driven or slow processing scenarios

Parameters

mode	SPI_TRANSFER_FLOW_NORMAL for continuous flow (no read requirement); SPI_TRANSFER_FLOW_WAIT_FOR_READ to require read before new transmit.

Note

This setting applies to Host mode (MSTR=1).

In Client mode, this field is not used.

Wait-for-Read mode can reduce throughput but improves data integrity.

See also

SPI0_Receive() to read receive data.

SPI0_RxIsReady() to check if receive data is available.

SPI0_TransferIsComplete()

bool SPI0_TransferIsComplete

(

void

)

Check if SPI transmit shift register is empty.

Tests the TXEMPTY (Transmit Shift Register Empty) flag in SPI_SR to determine if all data has been transmitted and the shift register is idle. TXEMPTY is set when both the Transmit Data Register (TDR) and the shift register are empty, meaning no data is being transmitted on the SPI bus.

Returns

true if TXEMPTY flag is set and the transmitter is completely idle; false otherwise.

Note

TXEMPTY is a subset of TDRE; if TXEMPTY is true, TDRE is also true.

Use this function before disabling SPI to ensure all data has been sent.

In interrupt mode, SPI_INTERRUPT_TXEMPTY can be enabled to signal transmission complete.

TXEMPTY is useful for synchronizing operations that must occur after transmission.

Unlike TDRE, TXEMPTY guarantees both registers are empty (no data in shift register).

See also

SPI0_TxIsReady() to check if Internal shift register is empty.

SPI0_TxIsReady()

bool SPI0_TxIsReady

(

void

)

Check if SPI transmitter is ready.

Tests the TDRE (Transmit Data Register Empty) flag in SPI_SR to determine if the transmitter is ready to accept new data. TDRE is set when data from SPI_TDR has been loaded into the internal shift register and transmission has started. TDRE is cleared when new data is written to SPI_TDR.

Returns

true if TDRE flag is set and SPI_TDR is ready for new data; false otherwise.

Note

When SPI is first enabled, TDRE is automatically set.

Use this function in polling mode before calling SPI0_Send().

In interrupt mode, SPI_INTERRUPT_TDRE can be enabled to signal readiness.

TDRE is cleared when SPI_TDR is written via SPI0_Send().

If TDRE is false, new data written to SPI_TDR will be queued and loaded after the current transmission completes.

See also

SPI0_Send() for writing transmit data.

SPI0_WriteProtectedIsViolated()

bool SPI0_WriteProtectedIsViolated

(

void

)

Check if a write protection violation has occurred.

Tests the WPVS (Write Protection Violation Status) bit in SPI_WPSR (Write Protection Status Register) to determine if an attempt to write to a protected register was detected. This flag is set when write protection is enabled (WPEN=1) and code attempts to modify a protected register.

Returns

true if a write protection violation was detected; false otherwise.

Note

A violation indicates:

• Write protection is enabled
• Code attempted to write to a protected register (SPI_MR, SPI_CR, SPI_CSR0-3)
• The write was blocked; register value was not changed

The violation flag typically remains set until explicitly cleared or the protection mode is reconfigured.

Use GetViolationSourceRegOffset() to determine which register caused the violation.

In safety-critical systems, violation attempts should trigger an alert/exception.

See also

SPI0_GetViolationSourceRegOffset() to identify which register was the target.

SPI0_DisableWriteProtection() to disable protection and allow modifications.

SPI0_WriteProtectionIsEnabled()

bool SPI0_WriteProtectionIsEnabled

(

void

)

Check if write protection is enabled.

Tests the WPEN (Write Protection Enable) bit in SPI_WPMR to determine if write protection is currently active. When enabled, protected registers cannot be modified.

Returns

true if write protection is enabled (WPEN = 1); false if disabled (WPEN = 0).

Note

Use this function to verify the current write protection state before attempting to modify protected registers.

If protection is enabled but modification is needed, call DisableWriteProtection().

This function does not indicate whether a violation has occurred; use WriteProtectedIsViolated() to check for violations.

See also

SPI0_EnableWriteProtection() to enable protection.

SPI0_DisableWriteProtection() to disable protection.

SPI0_WriteProtectedIsViolated() to detect violation attempts.