Driver API for XDMAC (plib_xdmac.h) More...

Data Structures
struct	XDMAC_CH_CONFIG
	XDMAC Channel Configuration Structure. More...

Typedefs
typedef void(*	XDMAC_CALLBACK) (uint32_t status)
	XDMAC Channel Callback Function Type.

Enumerations
enum	XDMAC_TRANSFER_EVENT { XDMAC_TRANSFER_NONE = 0 , XDMAC_TRANSFER_COMPLETE = 1 , XDMAC_TRANSFER_ERROR = 2 }

Functions
void	XDMAC_SetArbitrationWeights (uint8_t pw0, uint8_t pw1, uint8_t pw2, uint8_t pw3)
	Set the weighted round-robin arbitration weights for channel groups.

bool	XDMAC_ConfigureChannel (uint8_t channel, const XDMAC_CH_CONFIG *config)
	Configure an XDMAC channel for a specific transfer mode.

void	XDMAC_EnableChannel (uint8_t channel)
	Enable a specific XDMAC channel.

void	XDMAC_DisableChannel (uint8_t channel)
	Disable a specific XDMAC channel, ensuring pending transfers are completed or terminated.

void	XDMAC_SuspendChannel (uint8_t channel)
	Suspend a specific XDMAC channel, pausing its operation.

void	XDMAC_ResumeChannel (uint8_t channel)
	Resume a suspended XDMAC channel.

void	XDMAC_FlushChannel (uint8_t channel)
	Flush a specific XDMAC channel, terminating any pending transfers.

void	XDMAC_GenerateSoftwareTrigger (uint8_t channel)
	Trigger a software-initiated transfer for a channel configured for software requests.

void	XDMAC_EnableInterrupt (uint8_t channel, uint32_t interrupt_mask)
	Enable specified interrupt sources for a specific XDMAC channel.

void	XDMAC_EnableChannelInterrupt (uint8_t channel)
	Enable interrupts for a channel at the global level.

void	XDMAC_DisableInterrupt (uint8_t channel, uint32_t interrupt_mask)
	Disable specified interrupt sources for a specific XDMAC channel.

void	XDMAC_DisableChannelInterrupt (uint8_t channel)
	Disable all interrupts for a channel at the global level.

uint32_t	XDMAC_GetInterruptStatus (uint8_t channel)
	Returns the interrupt status flags for a specific XDMAC channel.

uint32_t	XDMAC_GetErrorStatus (uint8_t channel)
	Returns error status flags for a specific XDMAC channel.

void	XDMAC_SetCallbackHandler (uint8_t channel, XDMAC_CALLBACK callback)
	Register a callback function for a specific XDMAC channel interrupt source.

void	XDMAC_SoftwareResetChannel (uint8_t channel)
	Reset a specific XDMAC channel, clearing all configuration and status registers.

bool	XDMAC_StartTransfer (uint8_t channel, const void src_addr, const void dest_addr, size_t block_size)
	Perform a simple DMA transfer on a specific channel.

bool	XDMAC_ChannelIsBusy (uint8_t channel)
	Check if a specific XDMAC channel is currently busy with a transfer.

XDMAC_TRANSFER_EVENT	XDMAC_GetTransferStatus (uint8_t channel)
	Get the current transfer event status for a specific channel.

uint32_t	XDMAC_GetChannelSettings (uint8_t channel)
	Retrieve the current configuration register value for a specific channel.

void	XDMAC_SetChannelSettings (uint8_t channel, uint32_t setting)
	Update the configuration register for a specific channel.

void	XDMAC_SetBlockTransferCount (uint8_t channel, uint16_t length)
	Set the block length for a specific channel.

bool	XDMAC_StartLinkedListTransfer (uint8_t channel, uint32_t first_descriptor_address, const uint32_t *first_descriptor_control)
	Initiate a linked-list transfer on a specific channel.

void	XDMAC_SetSourceAddress (uint8_t channel, uint32_t src_addr)
	Set the source address for a specific channel.

void	XDMAC_SetDestinationAddress (uint8_t channel, uint32_t dst_addr)
	Set the destination address for a specific channel.

void	XDMAC_SetMicroblockLength (uint8_t channel, uint32_t length)
	Set the microblock length (number of data units per microblock) for a specific channel.

void	XDMAC_SetDataWidth (uint8_t channel, uint8_t data_width)
	Set the data width (beat size) for a specific channel.

void	XDMAC_SetBurstSize (uint8_t channel, uint8_t burst_size)
	Set the burst size for a specific channel.

void	XDMAC_EnableSrcAddrIncrement (uint8_t channel)
	Enable source address increment for a specific channel.

void	XDMAC_DisableSrcAddrIncrement (uint8_t channel)
	Disable source address increment for a specific channel (fixed address mode).

void	XDMAC_EnableDstAddrIncrement (uint8_t channel)
	Enable destination address increment for a specific channel.

void	XDMAC_DisableDstAddrIncrement (uint8_t channel)
	Disable destination address increment for a specific channel (fixed address mode).

void	XDMAC_SetTransferType (uint8_t channel, uint8_t transfer_type)
	Set the transfer type for a specific channel.

void	XDMAC_SetTriggerSource (uint8_t channel, uint8_t perid)
	Set the peripheral trigger source for a specific channel.

uint32_t	XDMAC_GetSourceAddress (uint8_t channel)
	Get the source address for a specific channel.

uint32_t	XDMAC_GetDestinationAddress (uint8_t channel)
	Get the destination address for a specific channel.

uint32_t	XDMAC_GetMicroblockLength (uint8_t channel)
	Get the microblock length for a specific channel.

Description

Driver API for XDMAC (plib_xdmac.h)

Usage Example

The following example demonstrates typical usage of the XDMAC peripheral:

 
#include "plib_xdmac.h"
#include <stdint.h>
#include <string.h>
 
#define XDMAC_TRANSFER_SIZE   1024U
#define XDMAC_TEST_CHANNEL    0U
#define XDMAC_TIMEOUT_CYCLES  1000000U
 
#define DCACHE_CLEAN_BY_ADDR(addr, sz)        SCB_CleanDCache_by_Addr((uint32_t *)(uintptr_t)(addr), (sz))
#define DCACHE_INVALIDATE_BY_ADDR(addr, sz)   SCB_InvalidateDCache_by_Addr((uint32_t *)(uintptr_t)(addr), (sz))
 
static uint8_t src_buff[XDMAC_TRANSFER_SIZE];
static uint8_t dst_buff[XDMAC_TRANSFER_SIZE];
 
/* Channel 0 (memory-to-memory) transfer status flags */
static volatile bool transfer_done = false;
static volatile bool transfer_error = false;
 
/* Channel 1 (UART TX) transfer status flags */
static volatile bool ch1_transfer_done = false;
static volatile bool ch1_transfer_error = false;
 
#define UART1_THR_ADDR          ((uint32_t)(uintptr_t)&UART1_REGS->UART_THR)
 
/* Use shared definitions from initialization.h if available, otherwise define locally */
#ifndef XDMAC_UART_CHANNEL
#define XDMAC_UART_CHANNEL      1U
#endif
#ifndef UART_DMA_BUFFER_SIZE
#define UART_DMA_BUFFER_SIZE    64U
#endif
 
static uint8_t _Alignas(32) uart_tx_buffer[UART_DMA_BUFFER_SIZE];
 
static void ch0_callback(uint32_t status)
{
    if ((status & XDMAC_CIS_BIS_Msk) != 0U)
    {
        /* Transfer complete */
        transfer_done = true;
    }
    else if ((status & (XDMAC_CIS_RBEIS_Msk | XDMAC_CIS_WBEIS_Msk | XDMAC_CIS_ROIS_Msk)) != 0U)
    {
        /* Transfer error occurred */
        transfer_error = true;
    }
    else
    {
        /* No action required */
    }
}
 
static void ch1_callback(uint32_t status)
{
    if ((status & XDMAC_CIS_BIS_Msk) != 0U)
    {
        /* UART TX transfer complete */
        ch1_transfer_done = true;
    }
    else if ((status & (XDMAC_CIS_RBEIS_Msk | XDMAC_CIS_WBEIS_Msk | XDMAC_CIS_ROIS_Msk)) != 0U)
    {
        /* UART TX transfer error occurred */
        ch1_transfer_error = true;
    }
    else
    {
        /* No action required */
    }
}
 
int32_t configure_xdmac(void)
{
    uint32_t i;
    uint32_t timeout;
    int32_t ret_val = -1;
 
    /* Initialize source buffer with incremental data */
    for (i = 0U; i < XDMAC_TRANSFER_SIZE; i++)
    {
        src_buff[i] = (uint8_t)i;
    }
 
    /* Clear destination buffer */
    (void)memset(dst_buff, 0, (size_t)XDMAC_TRANSFER_SIZE);
 
    /* Reset transfer flags */
    transfer_done = false;
    transfer_error = false;
 
    /* Register callback handler */
    XDMAC_SetCallbackHandler(XDMAC_TEST_CHANNEL, &ch0_callback);
 
    /* Configure channel using fine-grained APIs */
    XDMAC_SetSourceAddress(XDMAC_TEST_CHANNEL, (uint32_t)(uintptr_t)src_buff);
    XDMAC_SetDestinationAddress(XDMAC_TEST_CHANNEL, (uint32_t)(uintptr_t)dst_buff);
    XDMAC_SetMicroblockLength(XDMAC_TEST_CHANNEL, XDMAC_TRANSFER_SIZE);
 
    /* Set data width to BYTE (0) */
    XDMAC_SetDataWidth(XDMAC_TEST_CHANNEL, 0U);
 
    /* Set burst size to SINGLE (0) */
    XDMAC_SetBurstSize(XDMAC_TEST_CHANNEL, 0U);
 
    /* Set transfer type to memory-to-memory (0) */
    XDMAC_SetTransferType(XDMAC_TEST_CHANNEL, 0U);
 
    /* Enable source and destination address increment */
    XDMAC_EnableSrcAddrIncrement(XDMAC_TEST_CHANNEL);
    XDMAC_EnableDstAddrIncrement(XDMAC_TEST_CHANNEL);
 
    /* Clear residual block count from prior transfers (datasheet §34.4.4.1 step 7) */
    XDMAC_SetBlockTransferCount(XDMAC_TEST_CHANNEL, 0U);
 
    /* Clean source buffer from cache before DMA reads it */
    DCACHE_CLEAN_BY_ADDR(src_buff, (int32_t)XDMAC_TRANSFER_SIZE);
 
    /* Invalidate destination buffer cache before DMA writes to it */
    DCACHE_INVALIDATE_BY_ADDR(dst_buff, (int32_t)XDMAC_TRANSFER_SIZE);
 
    /* Enable channel interrupt at global level */
    XDMAC_EnableChannelInterrupt(XDMAC_TEST_CHANNEL);
 
    /* Enable block end interrupt (channel-level) */
    XDMAC_EnableInterrupt(XDMAC_TEST_CHANNEL, XDMAC_CIE_BIE_Msk);
 
    /* Enable the channel to start transfer.
     * For memory-to-memory transfers (TYPE=MEM_TRAN), the transfer starts
     * automatically when the channel is enabled. */
    XDMAC_EnableChannel(XDMAC_TEST_CHANNEL);
 
    /* Wait for transfer completion with timeout */
    timeout = XDMAC_TIMEOUT_CYCLES;
    while (timeout > 0U)
    {
        bool done = transfer_done;
        bool error = transfer_error;
        if (done || error) { break; }
        timeout--;
    }
 
    if (transfer_done == true)
    {
        /* Invalidate destination buffer after DMA completes (CPU reads updated data) */
        DCACHE_INVALIDATE_BY_ADDR(dst_buff, (int32_t)XDMAC_TRANSFER_SIZE);
 
        /* Verify data integrity */
        if (0 == memcmp(src_buff, dst_buff, (size_t)XDMAC_TRANSFER_SIZE))
        {
            ret_val = 0;
        }
    }
 
    return ret_val;
}
 
int32_t configure_xdmac_with_struct(void)
{
    uint32_t i;
    uint32_t timeout;
    XDMAC_CH_CONFIG config;
    bool result;
    int32_t ret_val = -1;
 
    /* Initialize source buffer with incremental data */
    for (i = 0U; i < XDMAC_TRANSFER_SIZE; i++)
    {
        src_buff[i] = (uint8_t)i;
    }
 
    /* Clear destination buffer */
    (void)memset(dst_buff, 0, (size_t)XDMAC_TRANSFER_SIZE);
 
    /* Reset transfer flags */
    transfer_done = false;
    transfer_error = false;
 
    /* Register callback handler */
    XDMAC_SetCallbackHandler(XDMAC_TEST_CHANNEL, &ch0_callback);
 
    /* Configure channel using structure */
    config.csa = (uint32_t)(uintptr_t)src_buff;
    config.cda = (uint32_t)(uintptr_t)dst_buff;
    config.cubc = XDMAC_TRANSFER_SIZE;
    config.cbc = 0U;
    config.cc = XDMAC_CC_TYPE_MEM_TRAN |
                XDMAC_CC_DWIDTH_BYTE |
                XDMAC_CC_SAM_INCREMENTED_AM |
                XDMAC_CC_DAM_INCREMENTED_AM |
                XDMAC_CC_MBSIZE_SINGLE;
    config.cds_msp = 0U;
    config.csus = 0U;
    config.cdus = 0U;
 
    result = XDMAC_ConfigureChannel(XDMAC_TEST_CHANNEL, &config);
 
    if (result == true)
    {
        /* Clean source buffer from cache before DMA reads it */
        DCACHE_CLEAN_BY_ADDR(src_buff, (int32_t)XDMAC_TRANSFER_SIZE);
 
        /* Invalidate destination buffer cache before DMA writes to it */
        DCACHE_INVALIDATE_BY_ADDR(dst_buff, (int32_t)XDMAC_TRANSFER_SIZE);
 
        /* Enable channel interrupt at global level */
        XDMAC_EnableChannelInterrupt(XDMAC_TEST_CHANNEL);
 
        /* Enable block end interrupt (channel-level) */
        XDMAC_EnableInterrupt(XDMAC_TEST_CHANNEL, XDMAC_CIE_BIE_Msk);
 
        /* Enable the channel to start transfer.
         * Memory-to-memory transfers start automatically on enable. */
        XDMAC_EnableChannel(XDMAC_TEST_CHANNEL);
 
        /* Wait for transfer completion with timeout */
        timeout = XDMAC_TIMEOUT_CYCLES;
        while (timeout > 0U)
        {
            bool done = transfer_done;
            bool error = transfer_error;
            if (done || error) { break; }
            timeout--;
        }
 
        if (transfer_done == true)
        {
            /* Invalidate destination buffer after DMA completes (CPU reads updated data) */
            DCACHE_INVALIDATE_BY_ADDR(dst_buff, (int32_t)XDMAC_TRANSFER_SIZE);
 
            /* Verify data integrity */
            if (0 == memcmp(src_buff, dst_buff, (size_t)XDMAC_TRANSFER_SIZE))
            {
                ret_val = 0;
            }
        }
    }
 
    return ret_val;
}
 
int32_t configure_xdmac_simple(void)
{
    uint32_t i;
    uint32_t timeout;
    bool result;
    int32_t ret_val = -1;
 
    /* Initialize source buffer with incremental data */
    for (i = 0U; i < XDMAC_TRANSFER_SIZE; i++)
    {
        src_buff[i] = (uint8_t)i;
    }
 
    /* Clear destination buffer */
    (void)memset(dst_buff, 0, (size_t)XDMAC_TRANSFER_SIZE);
 
    /* Reset transfer flags */
    transfer_done = false;
    transfer_error = false;
 
    /* Register callback handler */
    XDMAC_SetCallbackHandler(XDMAC_TEST_CHANNEL, &ch0_callback);
 
    /* Configure channel settings for memory-to-memory transfer */
    XDMAC_SetChannelSettings(XDMAC_TEST_CHANNEL,
                             XDMAC_CC_TYPE_MEM_TRAN |
                             XDMAC_CC_DWIDTH_BYTE |
                             XDMAC_CC_SAM_INCREMENTED_AM |
                             XDMAC_CC_DAM_INCREMENTED_AM |
                             XDMAC_CC_MBSIZE_SINGLE);
 
    /* Clean source buffer from cache before DMA reads it */
    DCACHE_CLEAN_BY_ADDR(src_buff, (int32_t)XDMAC_TRANSFER_SIZE);
 
    /* Invalidate destination buffer cache before DMA writes to it */
    DCACHE_INVALIDATE_BY_ADDR(dst_buff, (int32_t)XDMAC_TRANSFER_SIZE);
 
    /* Enable channel interrupt at global level */
    XDMAC_EnableChannelInterrupt(XDMAC_TEST_CHANNEL);
 
    /* Enable block end interrupt (channel-level) */
    XDMAC_EnableInterrupt(XDMAC_TEST_CHANNEL, XDMAC_CIE_BIE_Msk);
 
    /* Start the transfer using high-level API */
    result = XDMAC_StartTransfer(XDMAC_TEST_CHANNEL, src_buff, dst_buff, XDMAC_TRANSFER_SIZE);
 
    if (result == true)
    {
        /* Wait for transfer completion with timeout */
        timeout = XDMAC_TIMEOUT_CYCLES;
        while (timeout > 0U)
        {
            bool done = transfer_done;
            bool error = transfer_error;
            if (done || error) { break; }
            timeout--;
        }
 
        if (transfer_done == true)
        {
            /* Invalidate destination buffer after DMA completes (CPU reads updated data) */
            DCACHE_INVALIDATE_BY_ADDR(dst_buff, (int32_t)XDMAC_TRANSFER_SIZE);
 
            /* Verify data integrity */
            if (0 == memcmp(src_buff, dst_buff, (size_t)XDMAC_TRANSFER_SIZE))
            {
                ret_val = 0;
            }
        }
    }
 
    return ret_val;
}
 
int32_t configure_xdmac_linked_list(void)
{
    uint32_t i;
    uint32_t timeout;
    uint32_t desc_control;
    bool result;
    int32_t ret_val = -1;
 
    /* Descriptor address variable */
    static uint32_t _Alignas(4) desc_address;
 
    /* Initialize source buffer with incremental data */
    for (i = 0U; i < XDMAC_TRANSFER_SIZE; i++)
    {
        src_buff[i] = (uint8_t)i;
    }
 
    /* Clear destination buffer */
    (void)memset(dst_buff, 0, (size_t)XDMAC_TRANSFER_SIZE);
 
    /* Reset transfer flags */
    transfer_done = false;
    transfer_error = false;
 
    /* Register callback handler */
    XDMAC_SetCallbackHandler(XDMAC_TEST_CHANNEL, &ch0_callback);
 
    /* Configure channel settings for memory-to-memory transfer */
    XDMAC_SetChannelSettings(XDMAC_TEST_CHANNEL,
                             XDMAC_CC_TYPE_MEM_TRAN |
                             XDMAC_CC_DWIDTH_BYTE |
                             XDMAC_CC_SAM_INCREMENTED_AM |
                             XDMAC_CC_DAM_INCREMENTED_AM |
                             XDMAC_CC_MBSIZE_SINGLE);
 
    /* Set source and destination addresses */
    XDMAC_SetSourceAddress(XDMAC_TEST_CHANNEL, (uint32_t)(uintptr_t)src_buff);
    XDMAC_SetDestinationAddress(XDMAC_TEST_CHANNEL, (uint32_t)(uintptr_t)dst_buff);
    XDMAC_SetMicroblockLength(XDMAC_TEST_CHANNEL, XDMAC_TRANSFER_SIZE);
 
    /* Set up descriptor - single transfer with no next (end of list) */
    desc_address = 0U;  /* No next descriptor */
 
    /* Descriptor control: NDE=0 (descriptor fetch disabled, single transfer) */
    desc_control = XDMAC_CNDC_NDE(0U);
 
    /* Clean source buffer from cache before DMA reads it */
    DCACHE_CLEAN_BY_ADDR(src_buff, (int32_t)XDMAC_TRANSFER_SIZE);
 
    /* Invalidate destination buffer cache before DMA writes to it */
    DCACHE_INVALIDATE_BY_ADDR(dst_buff, (int32_t)XDMAC_TRANSFER_SIZE);
 
    /* Enable channel interrupt at global level */
    XDMAC_EnableChannelInterrupt(XDMAC_TEST_CHANNEL);
 
    /* Enable list end interrupt (channel-level) for linked list completion */
    XDMAC_EnableInterrupt(XDMAC_TEST_CHANNEL, XDMAC_CIE_LIE_Msk | XDMAC_CIE_BIE_Msk);
 
    /* Start linked list transfer */
    result = XDMAC_StartLinkedListTransfer(XDMAC_TEST_CHANNEL,
                                           desc_address,
                                           &desc_control);
 
    if (result == true)
    {
        /* Wait for transfer completion with timeout */
        timeout = XDMAC_TIMEOUT_CYCLES;
        while (timeout > 0U)
        {
            bool done = transfer_done;
            bool error = transfer_error;
            if (done || error) { break; }
            timeout--;
        }
 
        if (transfer_done == true)
        {
            /* Invalidate destination buffer after DMA completes (CPU reads updated data) */
            DCACHE_INVALIDATE_BY_ADDR(dst_buff, (int32_t)XDMAC_TRANSFER_SIZE);
 
            /* Verify data integrity */
            if (0 == memcmp(src_buff, dst_buff, (size_t)XDMAC_TRANSFER_SIZE))
            {
                ret_val = 0;
            }
        }
    }
 
    return ret_val;
}
 
/* ============================= */
/* === Peripheral Transfer    === */
/* ============================= */
 
 
int32_t configure_xdmac_uart1_tx(const uint8_t *data, uint32_t length)
{
    uint32_t channel_config;
    uint32_t timeout;
    int32_t ret_val = -1;
 
    if ((data == NULL) || (length == 0U) || (length > UART_DMA_BUFFER_SIZE))
    {
        /* Invalid parameters */
    }
    else if (XDMAC_ChannelIsBusy(XDMAC_UART_CHANNEL) == true)
    {
        /* Channel busy - previous transfer still in progress */
    }
    else
    {
        /* Reset transfer flags */
        ch1_transfer_done = false;
        ch1_transfer_error = false;
 
        /* Copy data to aligned buffer */
        (void)memcpy(uart_tx_buffer, data, (size_t)length);
 
        /* Register callback handler for channel 1 */
        XDMAC_SetCallbackHandler(XDMAC_UART_CHANNEL, &ch1_callback);
 
        /* Configure source address (memory buffer) */
        XDMAC_SetSourceAddress(XDMAC_UART_CHANNEL, (uint32_t)(uintptr_t)uart_tx_buffer);
 
        /* Configure destination address (UART1 THR - fixed) */
        XDMAC_SetDestinationAddress(XDMAC_UART_CHANNEL, UART1_THR_ADDR);
 
        /* Set transfer length */
        XDMAC_SetMicroblockLength(XDMAC_UART_CHANNEL, length);
 
        /* Configure channel for memory-to-peripheral transfer:
         * - TYPE = PER_TRAN (peripheral transfer, synchronized mode)
         * - DSYNC = MEM2PER (memory-to-peripheral direction)
         * - SWREQ = HWR_CONNECTED (hardware request from peripheral)
         * - PERID = UART1_TX (peripheral identifier)
         * - DWIDTH = BYTE (8-bit data width for UART)
         * - SAM = INCREMENTED (source address increments)
         * - DAM = FIXED (destination address fixed - UART THR)
         * - MBSIZE = SINGLE (single burst, appropriate for UART)
         */
        channel_config = XDMAC_CC_TYPE_PER_TRAN |
                         XDMAC_CC_DSYNC_MEM2PER |
                         XDMAC_CC_SWREQ_HWR_CONNECTED |
                         XDMAC_CC_PERID_UART1_TX |
                         XDMAC_CC_DWIDTH_BYTE |
                         XDMAC_CC_SIF_AHB_IF0 |
                         XDMAC_CC_DIF_AHB_IF1 |
                         XDMAC_CC_CSIZE_CHK_1 |
                         XDMAC_CC_SAM_INCREMENTED_AM |
                         XDMAC_CC_DAM_FIXED_AM |
                         XDMAC_CC_MBSIZE_SINGLE;
 
        XDMAC_SetChannelSettings(XDMAC_UART_CHANNEL, channel_config);
 
        /* Clear block count (single block transfer) */
        XDMAC_SetBlockTransferCount(XDMAC_UART_CHANNEL, 0U);
 
        /* Clean source buffer from cache before DMA reads it */
        DCACHE_CLEAN_BY_ADDR(uart_tx_buffer, (int32_t)length);
 
        /* Enable channel interrupt at global level */
        XDMAC_EnableChannelInterrupt(XDMAC_UART_CHANNEL);
 
        /* Enable block end and error interrupts (channel-level) */
        XDMAC_EnableInterrupt(XDMAC_UART_CHANNEL,
                              XDMAC_CIE_BIE_Msk |
                              XDMAC_CIE_RBIE_Msk |
                              XDMAC_CIE_WBIE_Msk |
                              XDMAC_CIE_ROIE_Msk);
 
        /* Enable the channel - transfer starts when UART signals TX ready */
        XDMAC_EnableChannel(XDMAC_UART_CHANNEL);
 
        /* Wait for transfer completion with timeout */
        timeout = XDMAC_TIMEOUT_CYCLES;
        while (timeout > 0U)
        {
            bool done = ch1_transfer_done;
            bool error = ch1_transfer_error;
            if (done || error) { break; }
            timeout--;
        }
 
        if (ch1_transfer_done == true)
        {
            ret_val = 0;
        }
    }
 
    return ret_val;
}
 

Typedef Documentation

◆ XDMAC_CALLBACK

typedef void(* XDMAC_CALLBACK) (uint32_t status)

XDMAC Channel Callback Function Type.

Parameters

[in] status Interrupt status flags (from XDMAC_CISx)

Returns: None.

Enumeration Type Documentation

◆ XDMAC_TRANSFER_EVENT

enum XDMAC_TRANSFER_EVENT

Enumerator
XDMAC_TRANSFER_NONE
XDMAC_TRANSFER_COMPLETE
XDMAC_TRANSFER_ERROR

Function Documentation

◆ XDMAC_ChannelIsBusy()

bool XDMAC_ChannelIsBusy ( uint8_t channel )

Check if a specific XDMAC channel is currently busy with a transfer.

Note: This function checks BOTH the internal software busy flag AND the hardware XDMAC_GS status. It returns true only when a transfer was started via XDMAC_StartTransfer()/XDMAC_StartLinkedListTransfer() and has not yet completed.

Parameters

[in] channel Channel index (0–23)

Returns: true if channel is busy.; false if channel is idle or disabled.

◆ XDMAC_ConfigureChannel()

bool XDMAC_ConfigureChannel	(	uint8_t	channel,
		const XDMAC_CH_CONFIG *	config )

Configure an XDMAC channel for a specific transfer mode.

Note: This function disables the channel and waits for it to go idle before modifying registers, per datasheet requirements. The channel will be disabled even if validation fails (e.g., misaligned addresses).

Parameters

[in]	channel	Channel index (0–23)
[in]	config	Pointer to channel configuration structure

Returns: true if configuration succeeds.; false on error (channel is still disabled).

◆ XDMAC_DisableChannel()

void XDMAC_DisableChannel ( uint8_t channel )

Disable a specific XDMAC channel, ensuring pending transfers are completed or terminated.

Note: This function busy-waits (polls XDMAC_GS) until the hardware confirms the channel is actually disabled before returning. This is required per datasheet because channel disable is asynchronous.

Parameters

[in] channel Channel index (0–23)

Returns: None.

◆ XDMAC_DisableChannelInterrupt()

void XDMAC_DisableChannelInterrupt ( uint8_t channel )

Disable all interrupts for a channel at the global level.

Note: This configures global interrupt routing (GID register). Blocks ALL interrupts from this channel reaching the NVIC, regardless of individual source settings (CIE).

Parameters

[in] channel Channel index (0–23)

Returns: None.

◆ XDMAC_DisableDstAddrIncrement()

void XDMAC_DisableDstAddrIncrement ( uint8_t channel )

Disable destination address increment for a specific channel (fixed address mode).

Note: This function disables the channel and waits for it to go idle before applying new settings. Any in-flight transfer will be aborted.

Parameters

[in] channel Channel index (0–23)

Returns: None.

◆ XDMAC_DisableInterrupt()

void XDMAC_DisableInterrupt	(	uint8_t	channel,
		uint32_t	interrupt_mask )

Disable specified interrupt sources for a specific XDMAC channel.

Note: This configures channel-level interrupt sources (CID register). Disables specific event triggers while leaving global routing intact.

Parameters

[in]	channel	Channel index (0–23)
[in]	interrupt_mask	Bitmask of interrupt sources to disable (e.g., XDMAC_CID_BID_Msk, XDMAC_CID_LID_Msk)

Returns: None.

◆ XDMAC_DisableSrcAddrIncrement()

void XDMAC_DisableSrcAddrIncrement ( uint8_t channel )

Disable source address increment for a specific channel (fixed address mode).

Note: This function disables the channel and waits for it to go idle before applying new settings. Any in-flight transfer will be aborted.

Parameters

[in] channel Channel index (0–23)

Returns: None.

◆ XDMAC_EnableChannel()

void XDMAC_EnableChannel ( uint8_t channel )

Enable a specific XDMAC channel.

Note: This function busy-waits (polls XDMAC_GS) until the hardware confirms the channel is actually enabled before returning.

Parameters

[in] channel Channel index (0–23)

Returns: None.

◆ XDMAC_EnableChannelInterrupt()

void XDMAC_EnableChannelInterrupt ( uint8_t channel )

Enable interrupts for a channel at the global level.

Note: This configures global interrupt routing (GIE register). Controls WHETHER this channel's interrupts reach the NVIC. Both this AND XDMAC_EnableInterrupt() must be called for ISR to fire.

Parameters

[in] channel Channel index (0–23)

Returns: None.

◆ XDMAC_EnableDstAddrIncrement()

void XDMAC_EnableDstAddrIncrement ( uint8_t channel )

Enable destination address increment for a specific channel.

Note: This function disables the channel and waits for it to go idle before applying new settings. Any in-flight transfer will be aborted.

Parameters

[in] channel Channel index (0–23)

Returns: None.

◆ XDMAC_EnableInterrupt()

void XDMAC_EnableInterrupt	(	uint8_t	channel,
		uint32_t	interrupt_mask )

Enable specified interrupt sources for a specific XDMAC channel.

Note: This configures channel-level interrupt sources (CIE register). Controls WHICH events trigger interrupts: block end, list end, errors, etc. Both this AND XDMAC_EnableChannelInterrupt() must be called for ISR to fire.

Parameters

[in]	channel	Channel index (0–23)
[in]	interrupt_mask	Bitmask of interrupt sources to enable (e.g., XDMAC_CIE_BIE_Msk, XDMAC_CIE_LIE_Msk)

Returns: None.

◆ XDMAC_EnableSrcAddrIncrement()

void XDMAC_EnableSrcAddrIncrement ( uint8_t channel )

Enable source address increment for a specific channel.

Note: This function disables the channel and waits for it to go idle before applying new settings. Any in-flight transfer will be aborted.

Parameters

[in] channel Channel index (0–23)

Returns: None.

◆ XDMAC_FlushChannel()

void XDMAC_FlushChannel ( uint8_t channel )

Flush a specific XDMAC channel, terminating any pending transfers.

Parameters

[in] channel Channel index (0–23)

Returns: None.

◆ XDMAC_GenerateSoftwareTrigger()

void XDMAC_GenerateSoftwareTrigger ( uint8_t channel )

Trigger a software-initiated transfer for a channel configured for software requests.

Parameters

[in] channel Channel index (0–23)

Returns: None.

◆ XDMAC_GetChannelSettings()

uint32_t XDMAC_GetChannelSettings ( uint8_t channel )

Retrieve the current configuration register value for a specific channel.

Parameters

[in] channel Channel index (0–23)

Returns: Channel configuration register value (XDMAC_CC)

◆ XDMAC_GetDestinationAddress()

uint32_t XDMAC_GetDestinationAddress ( uint8_t channel )

Get the destination address for a specific channel.

Parameters

[in] channel Channel index (0–23)

Returns: Destination address

◆ XDMAC_GetErrorStatus()

uint32_t XDMAC_GetErrorStatus ( uint8_t channel )

Returns error status flags for a specific XDMAC channel.

Warning: This function reads XDMAC_CIS which is clear-on-read. Calling this function clears all interrupt/error status bits for the channel, affecting XDMAC_GetInterruptStatus(), XDMAC_GetTransferStatus(), and ISR.

Parameters

[in] channel Channel index (0–23)

Returns: Error status flags (RBEIS, WBEIS, ROIS bits only)

◆ XDMAC_GetInterruptStatus()

uint32_t XDMAC_GetInterruptStatus ( uint8_t channel )

Returns the interrupt status flags for a specific XDMAC channel.

Warning: This function reads XDMAC_CIS which is clear-on-read. Calling this function clears all interrupt status bits for the channel, affecting XDMAC_GetErrorStatus(), XDMAC_GetTransferStatus(), and ISR.

Parameters

[in] channel Channel index (0–23)

Returns: Interrupt status flags (see XDMAC_CISx fields)

◆ XDMAC_GetMicroblockLength()

uint32_t XDMAC_GetMicroblockLength ( uint8_t channel )

Get the microblock length for a specific channel.

Parameters

[in] channel Channel index (0–23)

Returns: Microblock length

◆ XDMAC_GetSourceAddress()

uint32_t XDMAC_GetSourceAddress ( uint8_t channel )

Get the source address for a specific channel.

Parameters

[in] channel Channel index (0–23)

Returns: Source address

◆ XDMAC_GetTransferStatus()

XDMAC_TRANSFER_EVENT XDMAC_GetTransferStatus ( uint8_t channel )

Get the current transfer event status for a specific channel.

Warning: This function reads XDMAC_CIS which is clear-on-read. Calling this function clears all interrupt/error status bits for the channel, affecting XDMAC_GetInterruptStatus(), XDMAC_GetErrorStatus(), and ISR.

Parameters

[in] channel Channel index (0–23)

Returns: XDMAC_TRANSFER_EVENT status (NONE, COMPLETE, ERROR)

◆ XDMAC_ResumeChannel()

void XDMAC_ResumeChannel ( uint8_t channel )

Resume a suspended XDMAC channel.

Parameters

[in] channel Channel index (0–23)

Returns: None.

◆ XDMAC_SetArbitrationWeights()

void XDMAC_SetArbitrationWeights	(	uint8_t	pw0,
		uint8_t	pw1,
		uint8_t	pw2,
		uint8_t	pw3 )

Set the weighted round-robin arbitration weights for channel groups.

Note: Each weight value (pw0-pw3) controls the arbitration weight for a group of 6 channels: pw0 for channels 0-5, pw1 for channels 6-11, pw2 for channels 12-17, pw3 for channels 18-23. Higher weight values give more priority. Valid range is 0-15 (4-bit field).

Parameters

[in]	pw0	Weight for channel group 0 (channels 0-5)
[in]	pw1	Weight for channel group 1 (channels 6-11)
[in]	pw2	Weight for channel group 2 (channels 12-17)
[in]	pw3	Weight for channel group 3 (channels 18-23)

Returns: None.

◆ XDMAC_SetBlockTransferCount()

void XDMAC_SetBlockTransferCount	(	uint8_t	channel,
		uint16_t	length )

Set the block length for a specific channel.

Note: This function disables the channel before updating the block length, which will abort any in-flight transfer on that channel.; The hardware interprets BLEN as (BLEN+1) microblocks per block transfer. A value of 0 means 1 microblock, a value of 1 means 2 microblocks, etc.

Parameters

[in]	channel	Channel index (0–23)
[in]	length	Block length value (valid range: 0–4095; values above 4095 are masked to fit the 12-bit BLEN field)

Returns: None.

◆ XDMAC_SetBurstSize()

void XDMAC_SetBurstSize	(	uint8_t	channel,
		uint8_t	burst_size )

Set the burst size for a specific channel.

Note: This function disables the channel and waits for it to go idle before applying new settings. Any in-flight transfer will be aborted.

Parameters

[in]	channel	Channel index (0–23)
[in]	burst_size	Burst size (0=SINGLE, 1=FOUR, 2=EIGHT, 3=SIXTEEN)

Returns: None.

◆ XDMAC_SetCallbackHandler()

void XDMAC_SetCallbackHandler	(	uint8_t	channel,
		XDMAC_CALLBACK	callback )

Register a callback function for a specific XDMAC channel interrupt source.

Note

For the callback to be invoked from XDMAC_Handler(), you must also call:

XDMAC_EnableChannelInterrupt() to enable global interrupt for the channel
XDMAC_EnableInterrupt() to enable the desired channel interrupt sources (e.g., XDMAC_CIE_BIE_Msk for block end, XDMAC_CIE_LIE_Msk for list end) Both are required for the ISR to fire.

Parameters

[in]	channel	Channel index (0–23)
[in]	callback	Callback function pointer

Returns: None.

◆ XDMAC_SetChannelSettings()

void XDMAC_SetChannelSettings	(	uint8_t	channel,
		uint32_t	setting )

Update the configuration register for a specific channel.

Note: This function disables the channel and waits for it to go idle before applying new settings. Any in-flight transfer will be aborted.

Parameters

[in]	channel	Channel index (0–23)
[in]	setting	New configuration register value

Returns: None.

◆ XDMAC_SetDataWidth()

void XDMAC_SetDataWidth	(	uint8_t	channel,
		uint8_t	data_width )

Set the data width (beat size) for a specific channel.

Note: This function disables the channel and waits for it to go idle before applying new settings. Any in-flight transfer will be aborted.

Parameters

[in]	channel	Channel index (0–23)
[in]	data_width	Data width (0=BYTE, 1=HALFWORD, 2=WORD). Values 0-2 only; the DWIDTH field in XDMAC_CC is 2 bits.

Returns: None.

◆ XDMAC_SetDestinationAddress()

void XDMAC_SetDestinationAddress	(	uint8_t	channel,
		uint32_t	dst_addr )

Set the destination address for a specific channel.

Note: This function disables the channel and waits for it to go idle before applying new settings. Any in-flight transfer will be aborted.

Parameters

[in]	channel	Channel index (0–23)
[in]	dst_addr	Destination address

Returns: None.

◆ XDMAC_SetMicroblockLength()

void XDMAC_SetMicroblockLength	(	uint8_t	channel,
		uint32_t	length )

Set the microblock length (number of data units per microblock) for a specific channel.

Note: This function disables the channel and waits for it to go idle before applying new settings. Any in-flight transfer will be aborted.

Parameters

[in]	channel	Channel index (0–23)
[in]	length	Microblock length (UBLEN field, valid range: 0–16,777,215; values above 0xFFFFFF are masked to fit the 24-bit field)

Returns: None.

◆ XDMAC_SetSourceAddress()

void XDMAC_SetSourceAddress	(	uint8_t	channel,
		uint32_t	src_addr )

Set the source address for a specific channel.

Note: This function disables the channel and waits for it to go idle before applying new settings. Any in-flight transfer will be aborted.

Parameters

[in]	channel	Channel index (0–23)
[in]	src_addr	Source address

Returns: None.

◆ XDMAC_SetTransferType()

void XDMAC_SetTransferType	(	uint8_t	channel,
		uint8_t	transfer_type )

Set the transfer type for a specific channel.

Note: This function disables the channel and waits for it to go idle before applying new settings. Any in-flight transfer will be aborted.

Parameters

[in]	channel	Channel index (0–23)
[in]	transfer_type	Transfer type (0=MEM_TRAN, 1=PER_TRAN)

Returns: None.

◆ XDMAC_SetTriggerSource()

void XDMAC_SetTriggerSource	(	uint8_t	channel,
		uint8_t	perid )

Set the peripheral trigger source for a specific channel.

Note: This function disables the channel and waits for it to go idle before applying new settings. Any in-flight transfer will be aborted.

Parameters

[in]	channel	Channel index (0–23)
[in]	perid	Peripheral identifier for hardware handshaking

Returns: None.

◆ XDMAC_SoftwareResetChannel()

void XDMAC_SoftwareResetChannel ( uint8_t channel )

Reset a specific XDMAC channel, clearing all configuration and status registers.

Parameters

[in] channel Channel index (0–23)

Returns: None.

◆ XDMAC_StartLinkedListTransfer()

bool XDMAC_StartLinkedListTransfer	(	uint8_t	channel,
		uint32_t	first_descriptor_address,
		const uint32_t *	first_descriptor_control )

Initiate a linked-list transfer on a specific channel.

Note: NDAIF is hardcoded to 1 (AHB_IF1) for descriptor fetches. If your system requires a different interface, modify this function or use direct register access.

Parameters

[in]	channel	Channel index (0–23)
[in]	first_descriptor_address	Address of the first descriptor in the linked list
[in]	first_descriptor_control	Pointer to descriptor control configuration

Returns: true if linked-list transfer is initiated successfully.; false on error or if channel is busy.

◆ XDMAC_StartTransfer()

bool XDMAC_StartTransfer	(	uint8_t	channel,
		const void *	src_addr,
		const void *	dest_addr,
		size_t	block_size )

Perform a simple DMA transfer on a specific channel.

Note: The channel configuration register (XDMAC_CC) must be pre-configured before calling this function using XDMAC_ConfigureChannel(), XDMAC_SetChannelSettings(), or the fine-grained setter APIs (XDMAC_SetDataWidth, XDMAC_SetBurstSize, etc.). This function only sets the source address (CSA), destination address (CDA), microblock length (CUBC), and block count (CBC).

Parameters

[in]	channel	Channel index (0–23)
[in]	src_addr	Source address pointer
[in]	dest_addr	Destination address pointer
[in]	block_size	Number of data units to transfer

Returns: true if transfer is initiated successfully.; false on error or if channel is busy.

◆ XDMAC_SuspendChannel()

void XDMAC_SuspendChannel ( uint8_t channel )

Suspend a specific XDMAC channel, pausing its operation.

Parameters

[in] channel Channel index (0–23)

Returns: None.

Data Structures

Typedefs

Enumerations

Functions

Description

Usage Example

Typedef Documentation

◆ XDMAC_CALLBACK

Enumeration Type Documentation

◆ XDMAC_TRANSFER_EVENT

Function Documentation

◆ XDMAC_ChannelIsBusy()

◆ XDMAC_ConfigureChannel()

◆ XDMAC_DisableChannel()

◆ XDMAC_DisableChannelInterrupt()

◆ XDMAC_DisableDstAddrIncrement()

◆ XDMAC_DisableInterrupt()

◆ XDMAC_DisableSrcAddrIncrement()

◆ XDMAC_EnableChannel()

◆ XDMAC_EnableChannelInterrupt()

◆ XDMAC_EnableDstAddrIncrement()

◆ XDMAC_EnableInterrupt()

◆ XDMAC_EnableSrcAddrIncrement()

◆ XDMAC_FlushChannel()

◆ XDMAC_GenerateSoftwareTrigger()

◆ XDMAC_GetChannelSettings()

◆ XDMAC_GetDestinationAddress()

◆ XDMAC_GetErrorStatus()

◆ XDMAC_GetInterruptStatus()

◆ XDMAC_GetMicroblockLength()

◆ XDMAC_GetSourceAddress()

◆ XDMAC_GetTransferStatus()

◆ XDMAC_ResumeChannel()

◆ XDMAC_SetArbitrationWeights()

◆ XDMAC_SetBlockTransferCount()

◆ XDMAC_SetBurstSize()

◆ XDMAC_SetCallbackHandler()

◆ XDMAC_SetChannelSettings()

◆ XDMAC_SetDataWidth()

◆ XDMAC_SetDestinationAddress()

◆ XDMAC_SetMicroblockLength()

◆ XDMAC_SetSourceAddress()

◆ XDMAC_SetTransferType()

◆ XDMAC_SetTriggerSource()

◆ XDMAC_SoftwareResetChannel()

◆ XDMAC_StartLinkedListTransfer()

◆ XDMAC_StartTransfer()

◆ XDMAC_SuspendChannel()