UUID_LCK (aka EFUSE_SECCFG0_UUID_LCK, SECCFG0_UUID_LCK)	Programming lock bits for Unique ID fuses
UUID_LCK (aka EFUSE_SECCFG0_UUID_LCK, SECCFG0_UUID_LCK) = 0	Unique ID is not locked
UUID_LCK (aka EFUSE_SECCFG0_UUID_LCK, SECCFG0_UUID_LCK) = 1	Unique ID is locked and cannot be programmed
UUID_LCK (aka EFUSE_SECCFG0_UUID_LCK, SECCFG0_UUID_LCK) = 2	Unique ID is locked and cannot be programmed
UUID_LCK (aka EFUSE_SECCFG0_UUID_LCK, SECCFG0_UUID_LCK) = 3	Unique ID is locked and cannot be programmed

DEBUG_LCK (aka EFUSE_SECCFG0_DEBUG_LCK, SECCFG0_DEBUG_LCK)	Lock bits for debug/programming
DEBUG_LCK (aka EFUSE_SECCFG0_DEBUG_LCK, SECCFG0_DEBUG_LCK) = 0	Debug is not locked
DEBUG_LCK (aka EFUSE_SECCFG0_DEBUG_LCK, SECCFG0_DEBUG_LCK) = 1	Debug is locked
DEBUG_LCK (aka EFUSE_SECCFG0_DEBUG_LCK, SECCFG0_DEBUG_LCK) = 2	Debug is locked
DEBUG_LCK (aka EFUSE_SECCFG0_DEBUG_LCK, SECCFG0_DEBUG_LCK) = 3	Debug is locked

ROOT_KEY_LCK (aka EFUSE_SECCFG1_ROOT_KEY_LCK, SECCFG1_ROOT_KEY_LCK)	Lock bits for storage root Key
ROOT_KEY_LCK (aka EFUSE_SECCFG1_ROOT_KEY_LCK, SECCFG1_ROOT_KEY_LCK) = 0	Storage root key is not locked
ROOT_KEY_LCK (aka EFUSE_SECCFG1_ROOT_KEY_LCK, SECCFG1_ROOT_KEY_LCK) = 1	Storage root key is locked and cannot be programmed
ROOT_KEY_LCK (aka EFUSE_SECCFG1_ROOT_KEY_LCK, SECCFG1_ROOT_KEY_LCK) = 2	Storage root key is locked and cannot be programmed
ROOT_KEY_LCK (aka EFUSE_SECCFG1_ROOT_KEY_LCK, SECCFG1_ROOT_KEY_LCK) = 3	Storage root key is locked and cannot be programmed

BOOT_KEY_LCK (aka EFUSE_SECCFG1_BOOT_KEY_LCK, SECCFG1_BOOT_KEY_LCK)	Lock bits for Secure Boot/OTA Key
BOOT_KEY_LCK (aka EFUSE_SECCFG1_BOOT_KEY_LCK, SECCFG1_BOOT_KEY_LCK) = 0	Secure boot key is not locked
BOOT_KEY_LCK (aka EFUSE_SECCFG1_BOOT_KEY_LCK, SECCFG1_BOOT_KEY_LCK) = 1	Secure boot key is locked and cannot be programmed
BOOT_KEY_LCK (aka EFUSE_SECCFG1_BOOT_KEY_LCK, SECCFG1_BOOT_KEY_LCK) = 2	Secure boot key is locked and cannot be programmed
BOOT_KEY_LCK (aka EFUSE_SECCFG1_BOOT_KEY_LCK, SECCFG1_BOOT_KEY_LCK) = 3	Secure boot key is locked and cannot be programmed

PATCH_LCK (aka EFUSE_SECCFG1_PATCH_LCK, SECCFG1_PATCH_LCK)	Lock bits for patch
PATCH_LCK (aka EFUSE_SECCFG1_PATCH_LCK, SECCFG1_PATCH_LCK) = 0	Patch config and code are not locked
PATCH_LCK (aka EFUSE_SECCFG1_PATCH_LCK, SECCFG1_PATCH_LCK) = 1	Patch config and code are locked and cannot be programmed
PATCH_LCK (aka EFUSE_SECCFG1_PATCH_LCK, SECCFG1_PATCH_LCK) = 2	Patch config and code are locked and cannot be programmed
PATCH_LCK (aka EFUSE_SECCFG1_PATCH_LCK, SECCFG1_PATCH_LCK) = 3	Patch config and code are locked and cannot be programmed

ADD_BOOT_KEY (aka EFUSE_SECCFG2_ADD_BOOT_KEY, SECCFG2_ADD_BOOT_KEY)	Additional boot Key bit
ADD_BOOT_KEY (aka EFUSE_SECCFG2_ADD_BOOT_KEY, SECCFG2_ADD_BOOT_KEY) = SET
ADD_BOOT_KEY (aka EFUSE_SECCFG2_ADD_BOOT_KEY, SECCFG2_ADD_BOOT_KEY) = CLEAR

ANTIROLLBACKCOUNTER0_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER0_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER0_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER0_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER1_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER1_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER1_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER1_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER2_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER2_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER2_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER2_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER3_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER3_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER3_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER3_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER4_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER4_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER4_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER4_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER5_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER5_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER5_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER5_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER6_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER6_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER6_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER6_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER7_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER7_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER7_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER7_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER8_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER8_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER8_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER8_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER9_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER9_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER9_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER9_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER10_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER10_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER10_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER10_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER11_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER11_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER11_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER11_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER12_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER12_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER12_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER12_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER13_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER13_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER13_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER13_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER14_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER14_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER14_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER14_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER15_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER15_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER15_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER15_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER16_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER16_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER16_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER16_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER17_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER17_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER17_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER17_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER18_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER18_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER18_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER18_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER19_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER19_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER19_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER19_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER20_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER20_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER20_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER20_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER21_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER21_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER21_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER21_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER22_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER22_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER22_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER22_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER23_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER23_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER23_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER23_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER24_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER24_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER24_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER24_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER25_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER25_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER25_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER25_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER26_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER26_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER26_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER26_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER27_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER27_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER27_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER27_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER28_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER28_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER28_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER28_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER29_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER29_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER29_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER29_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER30_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER30_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER30_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER30_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

ANTIROLLBACKCOUNTER31_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER31_ANTIROLLBACKCOUNTER)	Anti rollback counter bits
ANTIROLLBACKCOUNTER31_ANTIROLLBACKCOUNTER (aka EFUSE_ANTIROLLBACKCOUNTER31_ANTIROLLBACKCOUNTER) = 00000000	Range is from 0 to 0xff

LIFECYCLECOUNTER0_LIFECYCLECOUNTER (aka EFUSE_LIFECYCLECOUNTER0_LIFECYCLECOUNTER)	Life cycle counter bits
LIFECYCLECOUNTER0_LIFECYCLECOUNTER (aka EFUSE_LIFECYCLECOUNTER0_LIFECYCLECOUNTER) = 00000000	Range is from 0 to 0xff

LIFECYCLECOUNTER1_LIFECYCLECOUNTER (aka EFUSE_LIFECYCLECOUNTER1_LIFECYCLECOUNTER)	Life cycle counter bits
LIFECYCLECOUNTER1_LIFECYCLECOUNTER (aka EFUSE_LIFECYCLECOUNTER1_LIFECYCLECOUNTER) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY0_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY0_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY0_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY0_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY1_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY1_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY1_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY1_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY2_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY2_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY2_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY2_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY3_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY3_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY3_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY3_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY4_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY4_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY4_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY4_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY5_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY5_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY5_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY5_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY6_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY6_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY6_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY6_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY7_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY7_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY7_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY7_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY8_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY8_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY8_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY8_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY9_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY9_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY9_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY9_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY10_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY10_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY10_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY10_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY11_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY11_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY11_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY11_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY12_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY12_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY12_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY12_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY13_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY13_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY13_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY13_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY14_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY14_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY14_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY14_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY15_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY15_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY15_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY15_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY16_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY16_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY16_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY16_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY17_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY17_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY17_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY17_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY18_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY18_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY18_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY18_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY19_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY19_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY19_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY19_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY20_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY20_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY20_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY20_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY21_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY21_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY21_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY21_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY22_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY22_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY22_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY22_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY23_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY23_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY23_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY23_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY24_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY24_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY24_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY24_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY25_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY25_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY25_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY25_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY26_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY26_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY26_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY26_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY27_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY27_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY27_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY27_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY28_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY28_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY28_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY28_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY29_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY29_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY29_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY29_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY30_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY30_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY30_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY30_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY31_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY31_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY31_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY31_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY32_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY32_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY32_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY32_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY33_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY33_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY33_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY33_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY34_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY34_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY34_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY34_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY35_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY35_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY35_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY35_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY36_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY36_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY36_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY36_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY37_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY37_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY37_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY37_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY38_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY38_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY38_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY38_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY39_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY39_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY39_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY39_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY40_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY40_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY40_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY40_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY41_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY41_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY41_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY41_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY42_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY42_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY42_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY42_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY43_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY43_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY43_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY43_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY44_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY44_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY44_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY44_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY45_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY45_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY45_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY45_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY46_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY46_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY46_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY46_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

SECUREBOOTKEY47_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY47_SECUREBOOTKEY)	Secure boot key bits
SECUREBOOTKEY47_SECUREBOOTKEY (aka EFUSE_SECUREBOOTKEY47_SECUREBOOTKEY) = 00000000	Range is from 0 to 0xff

UUID0_UUID (aka EFUSE_UUID0_UUID)	Unique ID bits
UUID0_UUID (aka EFUSE_UUID0_UUID) = 00000000	Range is from 0 to 0xff

UUID1_UUID (aka EFUSE_UUID1_UUID)	Unique ID bits
UUID1_UUID (aka EFUSE_UUID1_UUID) = 00000000	Range is from 0 to 0xff

UUID2_UUID (aka EFUSE_UUID2_UUID)	Unique ID bits
UUID2_UUID (aka EFUSE_UUID2_UUID) = 00000000	Range is from 0 to 0xff

UUID3_UUID (aka EFUSE_UUID3_UUID)	Unique ID bits
UUID3_UUID (aka EFUSE_UUID3_UUID) = 00000000	Range is from 0 to 0xff

UUID4_UUID (aka EFUSE_UUID4_UUID)	Unique ID bits
UUID4_UUID (aka EFUSE_UUID4_UUID) = 00000000	Range is from 0 to 0xff

UUID5_UUID (aka EFUSE_UUID5_UUID)	Unique ID bits
UUID5_UUID (aka EFUSE_UUID5_UUID) = 00000000	Range is from 0 to 0xff

UUID6_UUID (aka EFUSE_UUID6_UUID)	Unique ID bits
UUID6_UUID (aka EFUSE_UUID6_UUID) = 00000000	Range is from 0 to 0xff

UUID7_UUID (aka EFUSE_UUID7_UUID)	Unique ID bits
UUID7_UUID (aka EFUSE_UUID7_UUID) = 00000000	Range is from 0 to 0xff

UUID8_UUID (aka EFUSE_UUID8_UUID)	Unique ID bits
UUID8_UUID (aka EFUSE_UUID8_UUID) = 00000000	Range is from 0 to 0xff

UUID9_UUID (aka EFUSE_UUID9_UUID)	Unique ID bits
UUID9_UUID (aka EFUSE_UUID9_UUID) = 00000000	Range is from 0 to 0xff

UUID10_UUID (aka EFUSE_UUID10_UUID)	Unique ID bits
UUID10_UUID (aka EFUSE_UUID10_UUID) = 00000000	Range is from 0 to 0xff

UUID11_UUID (aka EFUSE_UUID11_UUID)	Unique ID bits
UUID11_UUID (aka EFUSE_UUID11_UUID) = 00000000	Range is from 0 to 0xff

UUID12_UUID (aka EFUSE_UUID12_UUID)	Unique ID bits
UUID12_UUID (aka EFUSE_UUID12_UUID) = 00000000	Range is from 0 to 0xff

UUID13_UUID (aka EFUSE_UUID13_UUID)	Unique ID bits
UUID13_UUID (aka EFUSE_UUID13_UUID) = 00000000	Range is from 0 to 0xff

UUID14_UUID (aka EFUSE_UUID14_UUID)	Unique ID bits
UUID14_UUID (aka EFUSE_UUID14_UUID) = 00000000	Range is from 0 to 0xff

UUID15_UUID (aka EFUSE_UUID15_UUID)	Unique ID bits
UUID15_UUID (aka EFUSE_UUID15_UUID) = 00000000	Range is from 0 to 0xff

ALTFBCFG7 (aka fuses_ALTFBCFG7_ALTFBCFG7, ALTFBCFG7_ALTFBCFG7)	RESERVED
ALTFBCFG7 (aka fuses_ALTFBCFG7_ALTFBCFG7, ALTFBCFG7_ALTFBCFG7) = 00000000	Range is from 0 to 0xffffffff

ALTFBCFG6 (aka fuses_ALTFBCFG6_ALTFBCFG6, ALTFBCFG6_ALTFBCFG6)	RESERVED
ALTFBCFG6 (aka fuses_ALTFBCFG6_ALTFBCFG6, ALTFBCFG6_ALTFBCFG6) = 00000000	Range is from 0 to 0xffffffff

ALTFUSERID (aka fuses_ALTFUSERID_ALTFUSERID, ALTFUSERID_ALTFUSERID)	ALT USERID
ALTFUSERID (aka fuses_ALTFUSERID_ALTFUSERID, ALTFUSERID_ALTFUSERID) = 00000000	Range is from 0 to 0xffffffff

ALTDEVCFG4 (aka fuses_ALTDEVCFG4_ALTDEVCFG4, ALTDEVCFG4_ALTDEVCFG4)	ALT CFGCON4 Fuses
ALTDEVCFG4 (aka fuses_ALTDEVCFG4_ALTDEVCFG4, ALTDEVCFG4_ALTDEVCFG4) = 00000000	Range is from 0 to 0xffffffff

ALTDEVCFG2 (aka fuses_ALTDEVCFG2_ALTDEVCFG2, ALTDEVCFG2_ALTDEVCFG2)	ALT CFGCON2 Fuses
ALTDEVCFG2 (aka fuses_ALTDEVCFG2_ALTDEVCFG2, ALTDEVCFG2_ALTDEVCFG2) = 00000000	Range is from 0 to 0xffffffff

ALTDEVCFG1 (aka fuses_ALTDEVCFG1_ALTDEVCFG1, ALTDEVCFG1_ALTDEVCFG1)	ALT CFGCON1 Fuses
ALTDEVCFG1 (aka fuses_ALTDEVCFG1_ALTDEVCFG1, ALTDEVCFG1_ALTDEVCFG1) = 00000000	Range is from 0 to 0xffffffff

ALTDEVCFG0 (aka fuses_ALTDEVCFG0_ALTDEVCFG0, ALTDEVCFG0_ALTDEVCFG0)	ALT CFGCON0 Fuses
ALTDEVCFG0 (aka fuses_ALTDEVCFG0_ALTDEVCFG0, ALTDEVCFG0_ALTDEVCFG0) = 00000000	Range is from 0 to 0xffffffff

ALTFBCFG0 (aka fuses_ALTFBCFG0_ALTFBCFG0, ALTFBCFG0_ALTFBCFG0)	ALT NVR BCFG0
ALTFBCFG0 (aka fuses_ALTFBCFG0_ALTFBCFG0, ALTFBCFG0_ALTFBCFG0) = 00000000	Range is from 0 to 0xffffffff

ALTFCPN3 (aka fuses_ALTFCPN3_ALTFCPN3, ALTFCPN3_ALTFCPN3)	RESERVED
ALTFCPN3 (aka fuses_ALTFCPN3_ALTFCPN3, ALTFCPN3_ALTFCPN3) = 00000000	Range is from 0 to 0xffffffff

ALTFCPN2 (aka fuses_ALTFCPN2_ALTFCPN2, ALTFCPN2_ALTFCPN2)	RESERVED
ALTFCPN2 (aka fuses_ALTFCPN2_ALTFCPN2, ALTFCPN2_ALTFCPN2) = 00000000	Range is from 0 to 0xffffffff

ALTFCPN1 (aka fuses_ALTFCPN1_ALTFCPN1, ALTFCPN1_ALTFCPN1)	RESERVED
ALTFCPN1 (aka fuses_ALTFCPN1_ALTFCPN1, ALTFCPN1_ALTFCPN1) = 00000000	Range is from 0 to 0xffffffff

ALTFCPN0 (aka fuses_ALTFCPN0_ALTFCPN0, ALTFCPN0_ALTFCPN0)	ALT NVR CPN Register
ALTFCPN0 (aka fuses_ALTFCPN0_ALTFCPN0, ALTFCPN0_ALTFCPN0) = 00000000	Range is from 0 to 0xffffffff

FBCFG7 (aka fuses_FBCFG7_FBCFG7, FBCFG7_FBCFG7)	RESERVED
FBCFG7 (aka fuses_FBCFG7_FBCFG7, FBCFG7_FBCFG7) = 00000000	Range is from 0 to 0xffffffff

FBCFG6 (aka fuses_FBCFG6_FBCFG6, FBCFG6_FBCFG6)	RESERVED
FBCFG6 (aka fuses_FBCFG6_FBCFG6, FBCFG6_FBCFG6) = 00000000	Range is from 0 to 0xffffffff

USER_ID (aka fuses_FUSERID_USER_ID, FUSERID_USER_ID)	User unique ID, readable using the SWD USER_ID instruction
USER_ID (aka fuses_FUSERID_USER_ID, FUSERID_USER_ID) = 00000000	Range is from 0 to 0xffff

SOSCCFG (aka fuses_DEVCFG4_SOSCCFG, DEVCFG4_SOSCCFG)	SOSC Configuration
SOSCCFG (aka fuses_DEVCFG4_SOSCCFG, DEVCFG4_SOSCCFG) = 00000000	Range is from 0 to 0xff

RTCEVENT_SEL (aka fuses_DEVCFG4_RTCEVENT_SEL, DEVCFG4_RTCEVENT_SEL)	RTC Event Selection
RTCEVENT_SEL (aka fuses_DEVCFG4_RTCEVENT_SEL, DEVCFG4_RTCEVENT_SEL) = ONE_SEC	1-Second Clock
RTCEVENT_SEL (aka fuses_DEVCFG4_RTCEVENT_SEL, DEVCFG4_RTCEVENT_SEL) = _32_KHZ (aka ALARM_PULSE)	Alarm Pulse

RTCEVENT_EN (aka fuses_DEVCFG4_RTCEVENT_EN, DEVCFG4_RTCEVENT_EN)	Pad Output Enable for MCHP legacy RTC event output
RTCEVENT_EN (aka fuses_DEVCFG4_RTCEVENT_EN, DEVCFG4_RTCEVENT_EN) = ON	Enable RTC Event
RTCEVENT_EN (aka fuses_DEVCFG4_RTCEVENT_EN, DEVCFG4_RTCEVENT_EN) = OFF	Disable RTC Event

VBKP_1KCSEL (aka fuses_DEVCFG4_VBKP_1KCSEL, DEVCFG4_VBKP_1KCSEL)	VDDBUKPCORE LPCLK Clock Selection
VBKP_1KCSEL (aka fuses_DEVCFG4_VBKP_1KCSEL, DEVCFG4_VBKP_1KCSEL) = _1K	Divide by 32 or 31.25 clock depending on VBKP_DIVSEL
VBKP_1KCSEL (aka fuses_DEVCFG4_VBKP_1KCSEL, DEVCFG4_VBKP_1KCSEL) = _32K	32kHz low power clock

VBKP_32KCSEL (aka fuses_DEVCFG4_VBKP_32KCSEL, DEVCFG4_VBKP_32KCSEL)	VDDBUKPCORE 32kHz clock source selection
VBKP_32KCSEL (aka fuses_DEVCFG4_VBKP_32KCSEL, DEVCFG4_VBKP_32KCSEL) = FRC	FRC
VBKP_32KCSEL (aka fuses_DEVCFG4_VBKP_32KCSEL, DEVCFG4_VBKP_32KCSEL) = POSC	POSC
VBKP_32KCSEL (aka fuses_DEVCFG4_VBKP_32KCSEL, DEVCFG4_VBKP_32KCSEL) = SOSC	SOSC
VBKP_32KCSEL (aka fuses_DEVCFG4_VBKP_32KCSEL, DEVCFG4_VBKP_32KCSEL) = LPRC	LPRC

VBKP_DIVSEL (aka fuses_DEVCFG4_VBKP_DIVSEL, DEVCFG4_VBKP_DIVSEL)	VDDBUKPCORE LPCLK Clock Divider Selection
VBKP_DIVSEL (aka fuses_DEVCFG4_VBKP_DIVSEL, DEVCFG4_VBKP_DIVSEL) = DIV_31_25	Divide by 31.25 (Recommended when LPCLK=32kHz)
VBKP_DIVSEL (aka fuses_DEVCFG4_VBKP_DIVSEL, DEVCFG4_VBKP_DIVSEL) = DIV_32	Divide-by 32 (Recommended when LPCLK=32.768kHz))

LPCLK_MOD (aka fuses_DEVCFG4_LPCLK_MOD, DEVCFG4_LPCLK_MOD)	LPCLK modifier in counter/delay mode
LPCLK_MOD (aka fuses_DEVCFG4_LPCLK_MOD, DEVCFG4_LPCLK_MOD) = DIV_1	Divide-by 1 (Recommended when LPCLK=32kHz)
LPCLK_MOD (aka fuses_DEVCFG4_LPCLK_MOD, DEVCFG4_LPCLK_MOD) = DIV_1_024	Divide-by 1.024 (Recommended when LPCLK=32.768kHz)

RTCEVTYPE (aka fuses_DEVCFG4_RTCEVTYPE, DEVCFG4_RTCEVTYPE)	RTC Event Type
RTCEVTYPE (aka fuses_DEVCFG4_RTCEVTYPE, DEVCFG4_RTCEVTYPE) = EVENT	RTC_EVENT
RTCEVTYPE (aka fuses_DEVCFG4_RTCEVTYPE, DEVCFG4_RTCEVTYPE) = OUT	RTC_OUT

CPEN_DLY (aka fuses_DEVCFG4_CPEN_DLY, DEVCFG4_CPEN_DLY)	Charge-pump ready digital delay
CPEN_DLY (aka fuses_DEVCFG4_CPEN_DLY, DEVCFG4_CPEN_DLY) = _1_LPRC	1 LPRC Clock Cycle Delay
CPEN_DLY (aka fuses_DEVCFG4_CPEN_DLY, DEVCFG4_CPEN_DLY) = _2_LPRC	2 LPRC Clock Cycle Delay
CPEN_DLY (aka fuses_DEVCFG4_CPEN_DLY, DEVCFG4_CPEN_DLY) = _3_LPRC	3 LPRC Clock Cycle Delay
CPEN_DLY (aka fuses_DEVCFG4_CPEN_DLY, DEVCFG4_CPEN_DLY) = _4_LPRC	4 LPRC Clock Cycle Delay
CPEN_DLY (aka fuses_DEVCFG4_CPEN_DLY, DEVCFG4_CPEN_DLY) = _5_LPRC	5 LPRC Clock Cycle Delay
CPEN_DLY (aka fuses_DEVCFG4_CPEN_DLY, DEVCFG4_CPEN_DLY) = _6_LPRC	6 LPRC Clock Cycle Delay
CPEN_DLY (aka fuses_DEVCFG4_CPEN_DLY, DEVCFG4_CPEN_DLY) = _7_LPRC	7 LPRC Clock Cycle Delay
CPEN_DLY (aka fuses_DEVCFG4_CPEN_DLY, DEVCFG4_CPEN_DLY) = _8_LPRC	8 LPRC Clock Cycle Delay

DSZPBOREN (aka fuses_DEVCFG4_DSZPBOREN, DEVCFG4_DSZPBOREN)	Deep Sleep Zero-Power BOR Enable
DSZPBOREN (aka fuses_DEVCFG4_DSZPBOREN, DEVCFG4_DSZPBOREN) = ON	Enabled
DSZPBOREN (aka fuses_DEVCFG4_DSZPBOREN, DEVCFG4_DSZPBOREN) = OFF	Disabled

DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS)	Deep Sleep Watchdog Timer Postscale Select
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS5	1:32(1ms)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS6	1:64(2.1ms)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS7	1:128(4.1ms)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS8	1:256(8.3ms)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS9	1:512(16.5ms)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS10	1:1024(33ms)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS11	1:2048(66.1ms)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS12	1:4096(132.1ms)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS13	1:8192(264.3ms)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS14	1:16384(528.5ms)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS15	1:32768(1.057s)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS16	1:65536(2.114s)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS17	1:2^17(4.288s)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS18	1:2^18(8.456s)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS19	1:2^19(16.912s)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS20	1:2^20(33.825s)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS21	1:2^21(67.7s)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS22	1:2^22(135.3s)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS23	1:2^23(4.5 minutes)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS24	1:2^24(9.0 minutes)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS25	1:2^25(18.0 minutes)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS26	1:2^26(36.1 minutes)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS27	1:2^27(72.2 minutes)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS28	1:2^28(2.4 hours)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS29	1:2^29(4.8 hours)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS30	1:2^30(9.6 hours)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS31	1:2^31(19.2 hours)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS32	1:2^32(38.5 hours)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS33	1:2^33(77.0 hours)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS34	1:2^34(6.4 days)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS35	1:2^35(12.8 days)
DSWDTPS (aka fuses_DEVCFG4_DSWDTPS, DEVCFG4_DSWDTPS) = DSPS36	1:2^36(25.7 days)

DSWDTOSC (aka fuses_DEVCFG4_DSWDTOSC, DEVCFG4_DSWDTOSC)	Deep Sleep Watchdog Timer Reference Clock Select
DSWDTOSC (aka fuses_DEVCFG4_DSWDTOSC, DEVCFG4_DSWDTOSC) = SOSC	Select SOSC as DSWDT Reference Clock
DSWDTOSC (aka fuses_DEVCFG4_DSWDTOSC, DEVCFG4_DSWDTOSC) = LPRC	Select LPRC as DSWDT Reference Clock

DSWDTEN (aka fuses_DEVCFG4_DSWDTEN, DEVCFG4_DSWDTEN)	Deep Sleep Watchdog Timer Enable
DSWDTEN (aka fuses_DEVCFG4_DSWDTEN, DEVCFG4_DSWDTEN) = ON	Enabled
DSWDTEN (aka fuses_DEVCFG4_DSWDTEN, DEVCFG4_DSWDTEN) = OFF	Disabled

DSEN (aka fuses_DEVCFG4_DSEN, DEVCFG4_DSEN)	Deep Sleep Bit Enable
DSEN (aka fuses_DEVCFG4_DSEN, DEVCFG4_DSEN) = ON	Enable DS Bit in DSCON
DSEN (aka fuses_DEVCFG4_DSEN, DEVCFG4_DSEN) = OFF	Disable DS Bit in DSCON

UVREGROVR (aka fuses_DEVCFG4_UVREGROVR, DEVCFG4_UVREGROVR)	ULPVREG Retention Mode Override
UVREGROVR (aka fuses_DEVCFG4_UVREGROVR, DEVCFG4_UVREGROVR) = FORCED	ULPVREG forced in retention mode
UVREGROVR (aka fuses_DEVCFG4_UVREGROVR, DEVCFG4_UVREGROVR) = CONTROLLED	ULPVREG controlled by XDS/DS FSM

LPOSCEN (aka fuses_DEVCFG4_LPOSCEN, DEVCFG4_LPOSCEN)	Low Power (Secondary) Oscillator Enable
LPOSCEN (aka fuses_DEVCFG4_LPOSCEN, DEVCFG4_LPOSCEN) = ON	Enabled
LPOSCEN (aka fuses_DEVCFG4_LPOSCEN, DEVCFG4_LPOSCEN) = OFF	Disable

RTCNTM_CSEL (aka fuses_DEVCFG4_RTCNTM_CSEL, DEVCFG4_RTCNTM_CSEL)	RTC Counter Mode Clock Select
RTCNTM_CSEL (aka fuses_DEVCFG4_RTCNTM_CSEL, DEVCFG4_RTCNTM_CSEL) = RAW	Raw 32kHz clock
RTCNTM_CSEL (aka fuses_DEVCFG4_RTCNTM_CSEL, DEVCFG4_RTCNTM_CSEL) = PROCESSED	Processed 32kHz clock

ACMP_CYCLE (aka fuses_DEVCFG2_ACMP_CYCLE, DEVCFG2_ACMP_CYCLE)	AC Comparator Result Wait Cycles
ACMP_CYCLE (aka fuses_DEVCFG2_ACMP_CYCLE, DEVCFG2_ACMP_CYCLE) = _32US	32us
ACMP_CYCLE (aka fuses_DEVCFG2_ACMP_CYCLE, DEVCFG2_ACMP_CYCLE) = _64US	64us
ACMP_CYCLE (aka fuses_DEVCFG2_ACMP_CYCLE, DEVCFG2_ACMP_CYCLE) = _96US	96us
ACMP_CYCLE (aka fuses_DEVCFG2_ACMP_CYCLE, DEVCFG2_ACMP_CYCLE) = _128US	128us
ACMP_CYCLE (aka fuses_DEVCFG2_ACMP_CYCLE, DEVCFG2_ACMP_CYCLE) = _160US	160us
ACMP_CYCLE (aka fuses_DEVCFG2_ACMP_CYCLE, DEVCFG2_ACMP_CYCLE) = _196US	196us
ACMP_CYCLE (aka fuses_DEVCFG2_ACMP_CYCLE, DEVCFG2_ACMP_CYCLE) = _224US	224us
ACMP_CYCLE (aka fuses_DEVCFG2_ACMP_CYCLE, DEVCFG2_ACMP_CYCLE) = _256US	256us

DMTINTV (aka fuses_DEVCFG2_DMTINTV, DEVCFG2_DMTINTV)	Dead Man Timer Count Window Interval
DMTINTV (aka fuses_DEVCFG2_DMTINTV, DEVCFG2_DMTINTV) = WIN_0	Window/Interval value is zero
DMTINTV (aka fuses_DEVCFG2_DMTINTV, DEVCFG2_DMTINTV) = WIN_1_2	Window/Interval value is 1/2 counter value
DMTINTV (aka fuses_DEVCFG2_DMTINTV, DEVCFG2_DMTINTV) = WIN_3_4	Window/Interval value is 3/4 counter value
DMTINTV (aka fuses_DEVCFG2_DMTINTV, DEVCFG2_DMTINTV) = WIN_7_8	Window/Interval value is 7/8 counter value
DMTINTV (aka fuses_DEVCFG2_DMTINTV, DEVCFG2_DMTINTV) = WIN_15_16	Window/Interval value is 15/16 counter value
DMTINTV (aka fuses_DEVCFG2_DMTINTV, DEVCFG2_DMTINTV) = WIN_31_32	Window/Interval value is 31/32 counter value
DMTINTV (aka fuses_DEVCFG2_DMTINTV, DEVCFG2_DMTINTV) = WIN_63_64	Window/Interval value is 63/64 counter value
DMTINTV (aka fuses_DEVCFG2_DMTINTV, DEVCFG2_DMTINTV) = WIN_127_128	Window/Interval value is 127/128 counter value

PMUTEST_VDD_EN (aka fuses_DEVCFG2_PMUTEST_VDD_EN, DEVCFG2_PMUTEST_VDD_EN)	PMU Test Output or VDD/2 Enable via ADC IE12
PMUTEST_VDD_EN (aka fuses_DEVCFG2_PMUTEST_VDD_EN, DEVCFG2_PMUTEST_VDD_EN) = PMU	PMU Test Output Monitor
PMUTEST_VDD_EN (aka fuses_DEVCFG2_PMUTEST_VDD_EN, DEVCFG2_PMUTEST_VDD_EN) = VDD_DIV_2	VDD_div_2 Monitor

POSCMOD (aka fuses_DEVCFG2_POSCMOD, DEVCFG2_POSCMOD)	Primary Oscillator Configuration
POSCMOD (aka fuses_DEVCFG2_POSCMOD, DEVCFG2_POSCMOD) = OFF
POSCMOD (aka fuses_DEVCFG2_POSCMOD, DEVCFG2_POSCMOD) = HS

WDTRMCS (aka fuses_DEVCFG2_WDTRMCS, DEVCFG2_WDTRMCS)	WDT RUN Mode Clock Select
WDTRMCS (aka fuses_DEVCFG2_WDTRMCS, DEVCFG2_WDTRMCS) = LPRC	LPRC
WDTRMCS (aka fuses_DEVCFG2_WDTRMCS, DEVCFG2_WDTRMCS) = SYSCLK	SYSCLK

SOSCSEL (aka fuses_DEVCFG2_SOSCSEL, DEVCFG2_SOSCSEL)	SOSC Selection Configuration
SOSCSEL (aka fuses_DEVCFG2_SOSCSEL, DEVCFG2_SOSCSEL) = XTAL
SOSCSEL (aka fuses_DEVCFG2_SOSCSEL, DEVCFG2_SOSCSEL) = SCLKI

WAKE2SPD (aka fuses_DEVCFG2_WAKE2SPD, DEVCFG2_WAKE2SPD)	2-Speed startup enabled in Sleep mode
WAKE2SPD (aka fuses_DEVCFG2_WAKE2SPD, DEVCFG2_WAKE2SPD) = ON
WAKE2SPD (aka fuses_DEVCFG2_WAKE2SPD, DEVCFG2_WAKE2SPD) = OFF

CKSWEN (aka fuses_DEVCFG2_CKSWEN, DEVCFG2_CKSWEN)	Software Clock Switching Enable
CKSWEN (aka fuses_DEVCFG2_CKSWEN, DEVCFG2_CKSWEN) = ON
CKSWEN (aka fuses_DEVCFG2_CKSWEN, DEVCFG2_CKSWEN) = OFF

FSCMEN (aka fuses_DEVCFG2_FSCMEN, DEVCFG2_FSCMEN)	Fail-Safe Clock Monitor Enable
FSCMEN (aka fuses_DEVCFG2_FSCMEN, DEVCFG2_FSCMEN) = ON
FSCMEN (aka fuses_DEVCFG2_FSCMEN, DEVCFG2_FSCMEN) = OFF

WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR)	Watchdog Timer Post-scale Select Run
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS1	1:1
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS2	1:2
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS4	1:4
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS8	1:8
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS16	1:16
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS32	1:32
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS64	1:64
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS128	1:128
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS256	1:256
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS512	1:512
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS1024	1:1024
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS2048	1:2048
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS4096	1:4096
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS8192	1:8192
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS16384	1:16384
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS32768	1:32768
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS65536	1:65536
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS131072	1:131072
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS262144	1:262144
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS524288	1:524288
WDTPSR (aka fuses_DEVCFG2_WDTPSR, DEVCFG2_WDTPSR) = PS1048576	1:1048576

WDTSPGM (aka fuses_DEVCFG2_WDTSPGM, DEVCFG2_WDTSPGM)	Watchdog Timer Stop during Flash Programming
WDTSPGM (aka fuses_DEVCFG2_WDTSPGM, DEVCFG2_WDTSPGM) = STOPS
WDTSPGM (aka fuses_DEVCFG2_WDTSPGM, DEVCFG2_WDTSPGM) = RUNS

WINDIS (aka fuses_DEVCFG2_WINDIS, DEVCFG2_WINDIS)	Windowed Watchdog Timer Disable
WINDIS (aka fuses_DEVCFG2_WINDIS, DEVCFG2_WINDIS) = NORMAL
WINDIS (aka fuses_DEVCFG2_WINDIS, DEVCFG2_WINDIS) = WINDOW

WDTEN (aka fuses_DEVCFG2_WDTEN, DEVCFG2_WDTEN)	Watchdog Timer Enable
WDTEN (aka fuses_DEVCFG2_WDTEN, DEVCFG2_WDTEN) = ON
WDTEN (aka fuses_DEVCFG2_WDTEN, DEVCFG2_WDTEN) = OFF

WDTWINSZ (aka fuses_DEVCFG2_WDTWINSZ, DEVCFG2_WDTWINSZ)	Watchdog Timer Window Size
WDTWINSZ (aka fuses_DEVCFG2_WDTWINSZ, DEVCFG2_WDTWINSZ) = WINSZ_25	Window size is 25%
WDTWINSZ (aka fuses_DEVCFG2_WDTWINSZ, DEVCFG2_WDTWINSZ) = WINSZ_37	Window size is 37.5%
WDTWINSZ (aka fuses_DEVCFG2_WDTWINSZ, DEVCFG2_WDTWINSZ) = WINSZ_50	Window size is 50%
WDTWINSZ (aka fuses_DEVCFG2_WDTWINSZ, DEVCFG2_WDTWINSZ) = WINSZ_75	Window size is 75%

DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT)	Dead Man Timer Count Select
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT8	2^8 (256)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT9	2^9 (512)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT10	2^10 (1024)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT11	2^11 (2048)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT12	2^12 (4096)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT13	2^13 (8192)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT14	2^14 (16384)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT15	2^15 (32768)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT16	2^16 (65536)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT17	2^17 (131072)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT18	2^18 (262144)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT19	2^19 (524288)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT20	2^20 (1048576)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT21	2^21 (2097152)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT22	2^22 (4194304)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT23	2^23 (8388608)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT24	2^24 (16777216)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT25	2^25 (33554432)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT26	2^26 (67108864)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT27	2^27 (134217728)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT28	2^28 (268435456)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT29	2^29 (536870912)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT30	2^30 (1073741824)
DMTCNT (aka fuses_DEVCFG2_DMTCNT, DEVCFG2_DMTCNT) = DMT31	2^31 (2147483648)

DMTEN (aka fuses_DEVCFG2_DMTEN, DEVCFG2_DMTEN)	Dead Man Timer Enable
DMTEN (aka fuses_DEVCFG2_DMTEN, DEVCFG2_DMTEN) = ON
DMTEN (aka fuses_DEVCFG2_DMTEN, DEVCFG2_DMTEN) = OFF

CAN0_PIN_EN (aka fuses_DEVCFG1_CAN0_PIN_EN, DEVCFG1_CAN0_PIN_EN)	CAN0 Pin Enable
CAN0_PIN_EN (aka fuses_DEVCFG1_CAN0_PIN_EN, DEVCFG1_CAN0_PIN_EN) = SET
CAN0_PIN_EN (aka fuses_DEVCFG1_CAN0_PIN_EN, DEVCFG1_CAN0_PIN_EN) = CLEAR

TRCEN (aka fuses_DEVCFG1_TRCEN, DEVCFG1_TRCEN)	Trace Enable
TRCEN (aka fuses_DEVCFG1_TRCEN, DEVCFG1_TRCEN) = OFF
TRCEN (aka fuses_DEVCFG1_TRCEN, DEVCFG1_TRCEN) = ON

CCL_OE (aka fuses_DEVCFG1_CCL_OE, DEVCFG1_CCL_OE)	CCL Pads (via PPS) Output Enable
CCL_OE (aka fuses_DEVCFG1_CCL_OE, DEVCFG1_CCL_OE) = OFF
CCL_OE (aka fuses_DEVCFG1_CCL_OE, DEVCFG1_CCL_OE) = ON

ZBTWKSYS (aka fuses_DEVCFG1_ZBTWKSYS, DEVCFG1_ZBTWKSYS)	ZBT Subsystem External Wake-up source
ZBTWKSYS (aka fuses_DEVCFG1_ZBTWKSYS, DEVCFG1_ZBTWKSYS) = OFF
ZBTWKSYS (aka fuses_DEVCFG1_ZBTWKSYS, DEVCFG1_ZBTWKSYS) = ON

CMP0_OE (aka fuses_DEVCFG1_CMP0_OE, DEVCFG1_CMP0_OE)	Analog Comparator-0 Output Enable
CMP0_OE (aka fuses_DEVCFG1_CMP0_OE, DEVCFG1_CMP0_OE) = OFF
CMP0_OE (aka fuses_DEVCFG1_CMP0_OE, DEVCFG1_CMP0_OE) = ON

CMP1_OE (aka fuses_DEVCFG1_CMP1_OE, DEVCFG1_CMP1_OE)	Analog Comparator-1 Output Enable
CMP1_OE (aka fuses_DEVCFG1_CMP1_OE, DEVCFG1_CMP1_OE) = OFF
CMP1_OE (aka fuses_DEVCFG1_CMP1_OE, DEVCFG1_CMP1_OE) = ON

QSPI_HSEN (aka fuses_DEVCFG1_QSPI_HSEN, DEVCFG1_QSPI_HSEN)	QSPI (Direct) Enable
QSPI_HSEN (aka fuses_DEVCFG1_QSPI_HSEN, DEVCFG1_QSPI_HSEN) = PPS
QSPI_HSEN (aka fuses_DEVCFG1_QSPI_HSEN, DEVCFG1_QSPI_HSEN) = DIRECT

SCOM0_HSEN (aka fuses_DEVCFG1_SCOM0_HSEN, DEVCFG1_SCOM0_HSEN)	SERCOM0 Direct (High Speed) Pin Enable
SCOM0_HSEN (aka fuses_DEVCFG1_SCOM0_HSEN, DEVCFG1_SCOM0_HSEN) = PPS
SCOM0_HSEN (aka fuses_DEVCFG1_SCOM0_HSEN, DEVCFG1_SCOM0_HSEN) = DIRECT

SCOM1_HSEN (aka fuses_DEVCFG1_SCOM1_HSEN, DEVCFG1_SCOM1_HSEN)	SERCOM1 Direct (High Speed) Pin Enable
SCOM1_HSEN (aka fuses_DEVCFG1_SCOM1_HSEN, DEVCFG1_SCOM1_HSEN) = PPS
SCOM1_HSEN (aka fuses_DEVCFG1_SCOM1_HSEN, DEVCFG1_SCOM1_HSEN) = DIRECT

SCOM2_HSEN (aka fuses_DEVCFG1_SCOM2_HSEN, DEVCFG1_SCOM2_HSEN)	SERCOM2 Direct (High Speed) Pin Enable
SCOM2_HSEN (aka fuses_DEVCFG1_SCOM2_HSEN, DEVCFG1_SCOM2_HSEN) = PPS
SCOM2_HSEN (aka fuses_DEVCFG1_SCOM2_HSEN, DEVCFG1_SCOM2_HSEN) = DIRECT

SMCLR (aka fuses_DEVCFG1_SMCLR, DEVCFG1_SMCLR)	Selects CRU handling of MCLR Control
SMCLR (aka fuses_DEVCFG1_SMCLR, DEVCFG1_SMCLR) = NO_POR
SMCLR (aka fuses_DEVCFG1_SMCLR, DEVCFG1_SMCLR) = FAUX_POR

QSCHE_EN (aka fuses_DEVCFG1_QSCHE_EN, DEVCFG1_QSCHE_EN)	QSPI Address Space Cache Attribute
QSCHE_EN (aka fuses_DEVCFG1_QSCHE_EN, DEVCFG1_QSCHE_EN) = OFF
QSCHE_EN (aka fuses_DEVCFG1_QSCHE_EN, DEVCFG1_QSCHE_EN) = ON

USBDMFTRIM (aka fuses_DEVCFG1_USBDMFTRIM, DEVCFG1_USBDMFTRIM)	USB DM Fall Trim fuse bits
USBDMFTRIM (aka fuses_DEVCFG1_USBDMFTRIM, DEVCFG1_USBDMFTRIM) = DEFAULT
USBDMFTRIM (aka fuses_DEVCFG1_USBDMFTRIM, DEVCFG1_USBDMFTRIM) = SLOWER
USBDMFTRIM (aka fuses_DEVCFG1_USBDMFTRIM, DEVCFG1_USBDMFTRIM) = SLIGH_FASTER
USBDMFTRIM (aka fuses_DEVCFG1_USBDMFTRIM, DEVCFG1_USBDMFTRIM) = SLIGH_SLOWER

USBDMRTRIM (aka fuses_DEVCFG1_USBDMRTRIM, DEVCFG1_USBDMRTRIM)	USB DM Rise Trim fuse bits
USBDMRTRIM (aka fuses_DEVCFG1_USBDMRTRIM, DEVCFG1_USBDMRTRIM) = DEFAULT
USBDMRTRIM (aka fuses_DEVCFG1_USBDMRTRIM, DEVCFG1_USBDMRTRIM) = SLIGH_FASTER
USBDMRTRIM (aka fuses_DEVCFG1_USBDMRTRIM, DEVCFG1_USBDMRTRIM) = FASTER
USBDMRTRIM (aka fuses_DEVCFG1_USBDMRTRIM, DEVCFG1_USBDMRTRIM) = SLOWER

USBDPFTRIM (aka fuses_DEVCFG1_USBDPFTRIM, DEVCFG1_USBDPFTRIM)	USB DP Fall Trim fuse bits
USBDPFTRIM (aka fuses_DEVCFG1_USBDPFTRIM, DEVCFG1_USBDPFTRIM) = DEFAULT
USBDPFTRIM (aka fuses_DEVCFG1_USBDPFTRIM, DEVCFG1_USBDPFTRIM) = SLOWER
USBDPFTRIM (aka fuses_DEVCFG1_USBDPFTRIM, DEVCFG1_USBDPFTRIM) = SLIGH_FASTER
USBDPFTRIM (aka fuses_DEVCFG1_USBDPFTRIM, DEVCFG1_USBDPFTRIM) = SLIGH_SLOWER

USBDPRTRIM (aka fuses_DEVCFG1_USBDPRTRIM, DEVCFG1_USBDPRTRIM)	USB DP Rise Trim fuse bits
USBDPRTRIM (aka fuses_DEVCFG1_USBDPRTRIM, DEVCFG1_USBDPRTRIM) = DEFAULT
USBDPRTRIM (aka fuses_DEVCFG1_USBDPRTRIM, DEVCFG1_USBDPRTRIM) = SLIGH_FASTER
USBDPRTRIM (aka fuses_DEVCFG1_USBDPRTRIM, DEVCFG1_USBDPRTRIM) = FASTER
USBDPRTRIM (aka fuses_DEVCFG1_USBDPRTRIM, DEVCFG1_USBDPRTRIM) = SLOWER

WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS)	Watchdog Timer Post-scale Select Sleep
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS1	1:1
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS2	1:2
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS4	1:4
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS8	1:8
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS16	1:16
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS32	1:32
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS64	1:64
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS128	1:128
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS256	1:256
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS512	1:512
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS1024	1:1024
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS2048	1:2048
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS4096	1:4096
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS8192	1:8192
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS16384	1:16384
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS32768	1:32768
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS65536	1:65536
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS131072	1:131072
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS262144	1:262144
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS524288	1:524288
WDTPSS (aka fuses_DEVCFG1_WDTPSS, DEVCFG1_WDTPSS) = PSS1048576	1:1048576

QSPIDDRM (aka fuses_DEVCFG1_QSPIDDRM, DEVCFG1_QSPIDDRM)	QSPI DDR Mode Clock Enable
QSPIDDRM (aka fuses_DEVCFG1_QSPIDDRM, DEVCFG1_QSPIDDRM) = ON
QSPIDDRM (aka fuses_DEVCFG1_QSPIDDRM, DEVCFG1_QSPIDDRM) = OFF

CLKZBREF (aka fuses_DEVCFG1_CLKZBREF, DEVCFG1_CLKZBREF)	External Reference Clock ZB Enable
CLKZBREF (aka fuses_DEVCFG1_CLKZBREF, DEVCFG1_CLKZBREF) = ON
CLKZBREF (aka fuses_DEVCFG1_CLKZBREF, DEVCFG1_CLKZBREF) = OFF

CAN1_PIN_EN (aka fuses_DEVCFG1_CAN1_PIN_EN, DEVCFG1_CAN1_PIN_EN)	CAN1 Pin Enable
CAN1_PIN_EN (aka fuses_DEVCFG1_CAN1_PIN_EN, DEVCFG1_CAN1_PIN_EN) = SET
CAN1_PIN_EN (aka fuses_DEVCFG1_CAN1_PIN_EN, DEVCFG1_CAN1_PIN_EN) = CLEAR

SWOEN (aka fuses_DEVCFG0_SWOEN, DEVCFG0_SWOEN)	SWO enable on 2-wire debug interface
SWOEN (aka fuses_DEVCFG0_SWOEN, DEVCFG0_SWOEN) = OFF
SWOEN (aka fuses_DEVCFG0_SWOEN, DEVCFG0_SWOEN) = ON

TROEN (aka fuses_DEVCFG0_TROEN, DEVCFG0_TROEN)	Trace Output Enable
TROEN (aka fuses_DEVCFG0_TROEN, DEVCFG0_TROEN) = OFF
TROEN (aka fuses_DEVCFG0_TROEN, DEVCFG0_TROEN) = ON

ADCPOVR (aka fuses_DEVCFG0_ADCPOVR, DEVCFG0_ADCPOVR)	ADC Charge Pump Override
ADCPOVR (aka fuses_DEVCFG0_ADCPOVR, DEVCFG0_ADCPOVR) = HW
ADCPOVR (aka fuses_DEVCFG0_ADCPOVR, DEVCFG0_ADCPOVR) = SW

CPENFILT (aka fuses_DEVCFG0_CPENFILT, DEVCFG0_CPENFILT)	ADC CP Filter Enable
CPENFILT (aka fuses_DEVCFG0_CPENFILT, DEVCFG0_CPENFILT) = OFF
CPENFILT (aka fuses_DEVCFG0_CPENFILT, DEVCFG0_CPENFILT) = ON

RTCIN0_ALTEN (aka fuses_DEVCFG0_RTCIN0_ALTEN, DEVCFG0_RTCIN0_ALTEN)	RTCIN0 Alternate Enable
RTCIN0_ALTEN (aka fuses_DEVCFG0_RTCIN0_ALTEN, DEVCFG0_RTCIN0_ALTEN) = PA3
RTCIN0_ALTEN (aka fuses_DEVCFG0_RTCIN0_ALTEN, DEVCFG0_RTCIN0_ALTEN) = PA9

RTCOUT_ALTEN (aka fuses_DEVCFG0_RTCOUT_ALTEN, DEVCFG0_RTCOUT_ALTEN)	RTCOUT Alternate Enable
RTCOUT_ALTEN (aka fuses_DEVCFG0_RTCOUT_ALTEN, DEVCFG0_RTCOUT_ALTEN) = PA4
RTCOUT_ALTEN (aka fuses_DEVCFG0_RTCOUT_ALTEN, DEVCFG0_RTCOUT_ALTEN) = PA10

USBSSEN (aka fuses_DEVCFG0_USBSSEN, DEVCFG0_USBSSEN)	USB Suspend Sleep Enable
USBSSEN (aka fuses_DEVCFG0_USBSSEN, DEVCFG0_USBSSEN) = SET
USBSSEN (aka fuses_DEVCFG0_USBSSEN, DEVCFG0_USBSSEN) = CLEAR

EPLLHWMD (aka fuses_DEVCFG0_EPLLHWMD, DEVCFG0_EPLLHWMD)	EWPLL HW Control Mode for PWDN and RESET
EPLLHWMD (aka fuses_DEVCFG0_EPLLHWMD, DEVCFG0_EPLLHWMD) = OFF
EPLLHWMD (aka fuses_DEVCFG0_EPLLHWMD, DEVCFG0_EPLLHWMD) = ON

UPLLHWMD (aka fuses_DEVCFG0_UPLLHWMD, DEVCFG0_UPLLHWMD)	UWPLL HW Control Mode for PWDN and RESET
UPLLHWMD (aka fuses_DEVCFG0_UPLLHWMD, DEVCFG0_UPLLHWMD) = OFF
UPLLHWMD (aka fuses_DEVCFG0_UPLLHWMD, DEVCFG0_UPLLHWMD) = ON

HPLUGDIS (aka fuses_DEVCFG0_HPLUGDIS, DEVCFG0_HPLUGDIS)	Hot Plugging Disable
HPLUGDIS (aka fuses_DEVCFG0_HPLUGDIS, DEVCFG0_HPLUGDIS) = OFF
HPLUGDIS (aka fuses_DEVCFG0_HPLUGDIS, DEVCFG0_HPLUGDIS) = ON

USBIDIO (aka fuses_DEVCFG0_USBIDIO, DEVCFG0_USBIDIO)	USB USBID Selection bit
USBIDIO (aka fuses_DEVCFG0_USBIDIO, DEVCFG0_USBIDIO) = SET
USBIDIO (aka fuses_DEVCFG0_USBIDIO, DEVCFG0_USBIDIO) = CLEAR

VBUSONIO (aka fuses_DEVCFG0_VBUSONIO, DEVCFG0_VBUSONIO)	USB VBUS_ON Selection bit
VBUSONIO (aka fuses_DEVCFG0_VBUSONIO, DEVCFG0_VBUSONIO) = SET
VBUSONIO (aka fuses_DEVCFG0_VBUSONIO, DEVCFG0_VBUSONIO) = CLEAR

SMBUS3EN2 (aka fuses_DEVCFG0_SMBUS3EN2, DEVCFG0_SMBUS3EN2)	SMBus3 Enable for SERCOM2
SMBUS3EN2 (aka fuses_DEVCFG0_SMBUS3EN2, DEVCFG0_SMBUS3EN2) = SET
SMBUS3EN2 (aka fuses_DEVCFG0_SMBUS3EN2, DEVCFG0_SMBUS3EN2) = CLEAR

PCM (aka fuses_DEVCFG0_PCM, DEVCFG0_PCM)	PCHE I/D Cacheable Mode
PCM (aka fuses_DEVCFG0_PCM, DEVCFG0_PCM) = CPU
PCM (aka fuses_DEVCFG0_PCM, DEVCFG0_PCM) = SFR

INT0E (aka fuses_DEVCFG0_INT0E, DEVCFG0_INT0E)	INT0 Enable
INT0E (aka fuses_DEVCFG0_INT0E, DEVCFG0_INT0E) = OFF
INT0E (aka fuses_DEVCFG0_INT0E, DEVCFG0_INT0E) = ON

INT0P (aka fuses_DEVCFG0_INT0P, DEVCFG0_INT0P)	INT0P Polarity
INT0P (aka fuses_DEVCFG0_INT0P, DEVCFG0_INT0P) = NEG
INT0P (aka fuses_DEVCFG0_INT0P, DEVCFG0_INT0P) = POS

CMEN (aka fuses_DEVCFG0_CMEN, DEVCFG0_CMEN)	SPA/DPA Countermeasures Enable
CMEN (aka fuses_DEVCFG0_CMEN, DEVCFG0_CMEN) = SET
CMEN (aka fuses_DEVCFG0_CMEN, DEVCFG0_CMEN) = CLEAR

FECCCON (aka fuses_DEVCFG0_FECCCON, DEVCFG0_FECCCON)	Flash ECC Control
FECCCON (aka fuses_DEVCFG0_FECCCON, DEVCFG0_FECCCON) = ON
FECCCON (aka fuses_DEVCFG0_FECCCON, DEVCFG0_FECCCON) = DYNAMIC
FECCCON (aka fuses_DEVCFG0_FECCCON, DEVCFG0_FECCCON) = OFF

FRECCDIS (aka fuses_DEVCFG0_FRECCDIS, DEVCFG0_FRECCDIS)	Flex RAM ECC Control
FRECCDIS (aka fuses_DEVCFG0_FRECCDIS, DEVCFG0_FRECCDIS) = OFF
FRECCDIS (aka fuses_DEVCFG0_FRECCDIS, DEVCFG0_FRECCDIS) = ON

PCSCMODE (aka fuses_FBCFG0_PCSCMODE, FBCFG0_PCSCMODE)	PCache Single cache Mode
PCSCMODE (aka fuses_FBCFG0_PCSCMODE, FBCFG0_PCSCMODE) = SINGLE	PCHE ICache Only.CPU Instructions (code, data) go to PCHE ONLY.
PCSCMODE (aka fuses_FBCFG0_PCSCMODE, FBCFG0_PCSCMODE) = DUAL	PCHE ICache and DCache. CPU opcodes go to PCEHE ICache port and data goes to PCHE

BINFOVALID (aka fuses_FBCFG0_BINFOVALID, FBCFG0_BINFOVALID)	BCFG info valid
BINFOVALID (aka fuses_FBCFG0_BINFOVALID, FBCFG0_BINFOVALID) = NOT_VALID	BCFG0 to BCFG7 is not valid.
BINFOVALID (aka fuses_FBCFG0_BINFOVALID, FBCFG0_BINFOVALID) = VALID	BCFG0 to BCFG7 is valid.

FCPN3 (aka fuses_FCPN3_FCPN3, FCPN3_FCPN3)	RESERVED
FCPN3 (aka fuses_FCPN3_FCPN3, FCPN3_FCPN3) = 00000000	Range is from 0 to 0xffffffff

FCPN2 (aka fuses_FCPN2_FCPN2, FCPN2_FCPN2)	RESERVED
FCPN2 (aka fuses_FCPN2_FCPN2, FCPN2_FCPN2) = 00000000	Range is from 0 to 0xffffffff

FCPN1 (aka fuses_FCPN1_FCPN1, FCPN1_FCPN1)	RESERVED
FCPN1 (aka fuses_FCPN1_FCPN1, FCPN1_FCPN1) = 00000000	Range is from 0 to 0xffffffff

CP (aka fuses_FCPN0_CP, FCPN0_CP)	Boot Code Protect
CP (aka fuses_FCPN0_CP, FCPN0_CP) = DISABLED	Protection Disabled
CP (aka fuses_FCPN0_CP, FCPN0_CP) = ENABLED	Protection Enabled